[FFmpeg-devel] [PATCH] Altivec split-radix FFT
Loren Merritt
lorenm
Fri Aug 28 18:48:08 CEST 2009
On Fri, 28 Aug 2009, M?ns Rullg?rd wrote:
> Reimar D?ffinger <Reimar.Doeffinger at gmx.de> writes:
>> On Fri, Aug 28, 2009 at 10:02:35AM +0200, Guillaume POIRIER wrote:
>>>
>>> It indeed now works on Linux/PPC64 and Linux/PPC32, but still not on OSX/PPC*.
>>>
>>> Do you think that gas' .macro functionalities could allow to make your
>>> ASM portable across both Linux and OSX, defining each register Rx as
>>> either rx on OSX, and x on all the other platforms that use FSF tools?
>>
>> It is preprocessed anyway, you can just define REG_1... REG_n in a
>> header and in include that in both C and asm files.
>
> I'd just #define r1 1 etc for the cases that prefer numbers over
> names.
Avoided .ifb.
Fixed register names (untested).
The manually unrolled list is ugly, but I can't find a gas equivalent to
yasm's ability to expand macros in macro names.
Are the other configure checks for ppc asm broken? Some use register names
and some don't, and I don't think this is what they're supposed to be
detecting.
When the first reg of an address is being a literal zero rather than a
register, should it be named?
Didn't change .rodata. Is there some version-dependent define for that?
Or same/another configure check?
--Loren Merritt
-------------- next part --------------
diff --git a/configure b/configure
index 5c13369..cbfc804 100755
--- a/configure
+++ b/configure
@@ -953,6 +953,7 @@ HAVE_LIST="
malloc_h
memalign
mkstemp
+ named_regs
pld
posix_memalign
round
@@ -2107,6 +2108,7 @@ elif enabled mips; then
elif enabled ppc; then
+ check_asm named_regs '"add r0, r0, r0"'
check_asm dcbzl '"dcbzl 0, 1"'
check_asm ppc4xx '"maclhw r10, r11, r12"'
check_asm xform_asm '"lwzx 0, %y0" :: "Z"(*(int*)0)'
diff --git a/libavcodec/Makefile b/libavcodec/Makefile
index 24e6af4..5a9113b 100644
--- a/libavcodec/Makefile
+++ b/libavcodec/Makefile
@@ -523,6 +523,7 @@ OBJS-$(HAVE_ALTIVEC) += ppc/check_altivec.o \
ppc/dsputil_altivec.o \
ppc/fdct_altivec.o \
ppc/fft_altivec.o \
+ ppc/fft_altivec_s.o \
ppc/float_altivec.o \
ppc/gmc_altivec.o \
ppc/idct_altivec.o \
diff --git a/libavcodec/fft.c b/libavcodec/fft.c
index a3f1151..d864f82 100644
--- a/libavcodec/fft.c
+++ b/libavcodec/fft.c
@@ -110,7 +110,6 @@ av_cold int ff_fft_init(FFTContext *s, int nbits, int inverse)
has_vectors = mm_support();
if (has_vectors & FF_MM_ALTIVEC) {
s->fft_calc = ff_fft_calc_altivec;
- split_radix = 0;
}
#endif
diff --git a/libavcodec/ppc/asm.S b/libavcodec/ppc/asm.S
new file mode 100644
index 0000000..d7d35fc
--- /dev/null
+++ b/libavcodec/ppc/asm.S
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2009 Loren Merritt
+ *
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "config.h"
+
+// Apple's assembler requires named registers, while FSF's requires bare numbers.
+#if !HAVE_NAMED_REGS
+.macro DEFINE_REG n
+.equiv r\n, \n
+.equiv f\n, \n
+.equiv v\n, \n
+.endm
+DEFINE_REG 0
+DEFINE_REG 1
+DEFINE_REG 2
+DEFINE_REG 3
+DEFINE_REG 4
+DEFINE_REG 5
+DEFINE_REG 6
+DEFINE_REG 7
+DEFINE_REG 8
+DEFINE_REG 9
+DEFINE_REG 10
+DEFINE_REG 11
+DEFINE_REG 12
+DEFINE_REG 13
+DEFINE_REG 14
+DEFINE_REG 15
+DEFINE_REG 16
+DEFINE_REG 17
+DEFINE_REG 18
+DEFINE_REG 19
+DEFINE_REG 20
+DEFINE_REG 21
+DEFINE_REG 22
+DEFINE_REG 23
+DEFINE_REG 24
+DEFINE_REG 25
+DEFINE_REG 26
+DEFINE_REG 27
+DEFINE_REG 28
+DEFINE_REG 29
+DEFINE_REG 30
+DEFINE_REG 31
+#endif
diff --git a/libavcodec/ppc/fft_altivec.c b/libavcodec/ppc/fft_altivec.c
index 7391131..c113820 100644
--- a/libavcodec/ppc/fft_altivec.c
+++ b/libavcodec/ppc/fft_altivec.c
@@ -1,8 +1,7 @@
/*
* FFT/IFFT transforms
* AltiVec-enabled
- * Copyright (c) 2003 Romain Dolbeau <romain at dolbeau.org>
- * Based on code Copyright (c) 2002 Fabrice Bellard
+ * Copyright (c) 2009 Loren Merritt
*
* This file is part of FFmpeg.
*
@@ -23,6 +22,7 @@
#include "libavcodec/dsputil.h"
#include "dsputil_ppc.h"
#include "util_altivec.h"
+#include "types_altivec.h"
/**
* Do a complex FFT with the parameters defined in ff_fft_init(). The
* input data must be permuted before with s->revtab table. No
@@ -30,106 +30,66 @@
* AltiVec-enabled
* This code assumes that the 'z' pointer is 16 bytes-aligned
* It also assumes all FFTComplex are 8 bytes-aligned pair of float
- * The code is exactly the same as the SSE version, except
- * that successive MUL + ADD/SUB have been merged into
- * fused multiply-add ('vec_madd' in altivec)
*/
-void ff_fft_calc_altivec(FFTContext *s, FFTComplex *z)
-{
-POWERPC_PERF_DECLARE(altivec_fft_num, s->nbits >= 6);
- register const vector float vczero = (const vector float)vec_splat_u32(0.);
-
- int ln = s->nbits;
- int j, np, np2;
- int nblocks, nloops;
- register FFTComplex *p, *q;
- FFTComplex *cptr, *cptr1;
- int k;
-
-POWERPC_PERF_START_COUNT(altivec_fft_num, s->nbits >= 6);
-
- np = 1 << ln;
-
- {
- vector float *r, a, b, a1, c1, c2;
-
- r = (vector float *)&z[0];
-
- c1 = vcii(p,p,n,n);
-
- if (s->inverse) {
- c2 = vcii(p,p,n,p);
- } else {
- c2 = vcii(p,p,p,n);
- }
-
- j = (np >> 2);
- do {
- a = vec_ld(0, r);
- a1 = vec_ld(sizeof(vector float), r);
-
- b = vec_perm(a,a,vcprmle(1,0,3,2));
- a = vec_madd(a,c1,b);
- /* do the pass 0 butterfly */
-
- b = vec_perm(a1,a1,vcprmle(1,0,3,2));
- b = vec_madd(a1,c1,b);
- /* do the pass 0 butterfly */
-
- /* multiply third by -i */
- b = vec_perm(b,b,vcprmle(2,3,1,0));
- /* do the pass 1 butterfly */
- vec_st(vec_madd(b,c2,a), 0, r);
- vec_st(vec_nmsub(b,c2,a), sizeof(vector float), r);
+extern FFTSample ff_cos_16[];
+// pointers to functions. but unlike function pointers on some PPC ABIs, these aren't function descriptors.
+extern void *ff_fft_dispatch_altivec[2][15];
- r += 2;
- } while (--j != 0);
+// convert from simd order to C order
+static void swizzle(vec_f *z, int n)
+{
+ int i;
+ n >>= 1;
+ for(i=0; i<n; i+=2) {
+ vec_f re = z[i];
+ vec_f im = z[i+1];
+ z[i] = vec_mergeh(re, im);
+ z[i+1] = vec_mergel(re, im);
}
- /* pass 2 .. ln-1 */
-
- nblocks = np >> 3;
- nloops = 1 << 2;
- np2 = np >> 1;
-
- cptr1 = s->exptab1;
- do {
- p = z;
- q = z + nloops;
- j = nblocks;
- do {
- cptr = cptr1;
- k = nloops >> 1;
- do {
- vector float a,b,c,t1;
-
- a = vec_ld(0, (float*)p);
- b = vec_ld(0, (float*)q);
-
- /* complex mul */
- c = vec_ld(0, (float*)cptr);
- /* cre*re cim*re */
- t1 = vec_madd(c, vec_perm(b,b,vcprmle(2,2,0,0)),vczero);
- c = vec_ld(sizeof(vector float), (float*)cptr);
- /* -cim*im cre*im */
- b = vec_madd(c, vec_perm(b,b,vcprmle(3,3,1,1)),t1);
-
- /* butterfly */
- vec_st(vec_add(a,b), 0, (float*)p);
- vec_st(vec_sub(a,b), 0, (float*)q);
-
- p += 2;
- q += 2;
- cptr += 4;
- } while (--k);
-
- p += nloops;
- q += nloops;
- } while (--j);
- cptr1 += nloops * 2;
- nblocks = nblocks >> 1;
- nloops = nloops << 1;
- } while (nblocks != 0);
+}
-POWERPC_PERF_STOP_COUNT(altivec_fft_num, s->nbits >= 6);
+void ff_fft_calc_altivec(FFTContext *s, FFTComplex *z)
+{
+ register vec_f v14 __asm__("v14") = {0,0,0,0};
+ register vec_f v15 __asm__("v15") = *(const vec_f*)ff_cos_16;
+ register vec_f v16 __asm__("v16") = {0, 0.38268343, M_SQRT1_2, 0.92387953};
+ register vec_f v17 __asm__("v17") = {-M_SQRT1_2, M_SQRT1_2, M_SQRT1_2,-M_SQRT1_2};
+ register vec_f v18 __asm__("v18") = { M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, M_SQRT1_2};
+ register vec_u8 v19 __asm__("v19") = vcprm(s0,3,2,1);
+ register vec_u8 v20 __asm__("v20") = vcprm(0,1,s2,s1);
+ register vec_u8 v21 __asm__("v21") = vcprm(2,3,s0,s3);
+ register vec_u8 v22 __asm__("v22") = vcprm(2,s3,3,s2);
+ register vec_u8 v23 __asm__("v23") = vcprm(0,1,s0,s1);
+ register vec_u8 v24 __asm__("v24") = vcprm(2,3,s2,s3);
+ register vec_u8 v25 __asm__("v25") = vcprm(2,3,0,1);
+ register vec_u8 v26 __asm__("v26") = vcprm(1,2,s3,s0);
+ register vec_u8 v27 __asm__("v27") = vcprm(0,3,s2,s1);
+ register vec_u8 v28 __asm__("v28") = vcprm(0,2,s1,s3);
+ register vec_u8 v29 __asm__("v29") = vcprm(1,3,s0,s2);
+ register FFTSample **cos_tabs __asm__("r12") = ff_cos_tabs;
+ register FFTComplex *zarg __asm__("r3") = z;
+ __asm__(
+ "mtctr %0 \n"
+#if HAVE_NAMED_REGS
+ "li r9,16 \n"
+ "subi r1,r1,%1 \n"
+ "bctrl \n"
+ "addi r1,r1,%1 \n"
+#else
+ "li 9,16 \n"
+ "subi 1,1,%1 \n"
+ "bctrl \n"
+ "addi 1,1,%1 \n"
+#endif
+ ::"r"(ff_fft_dispatch_altivec[1][s->nbits-2]), "i"(12*sizeof(void*)),
+ "r"(zarg), "r"(cos_tabs),
+ "v"(v14),"v"(v15),"v"(v16),"v"(v17),"v"(v18),"v"(v19),"v"(v20),"v"(v21),
+ "v"(v22),"v"(v23),"v"(v24),"v"(v25),"v"(v26),"v"(v27),"v"(v28),"v"(v29)
+ : "lr","ctr","r0","r4","r5","r6","r7","r8","r9","r10","r11",
+ "v0","v1","v2","v3","v4","v5","v6","v7","v8","v9","v10","v11","v12","v13"
+ );
+ if(s->nbits <= 4)
+ swizzle((vec_f*)z, 1<<s->nbits);
}
+
diff --git a/libavcodec/ppc/fft_altivec_s.S b/libavcodec/ppc/fft_altivec_s.S
new file mode 100644
index 0000000..038c9fe
--- /dev/null
+++ b/libavcodec/ppc/fft_altivec_s.S
@@ -0,0 +1,322 @@
+/*
+ * FFT transform with Altivec optimizations
+ * Copyright (c) 2009 Loren Merritt
+ *
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * These functions are not individually interchangeable with the C versions.
+ * While C takes arrays of FFTComplex, Altivec leaves intermediate results
+ * in blocks as convenient to the vector size.
+ * i.e. {4x real, 4x imaginary, 4x real, ...}
+ *
+ * I ignore standard calling convention.
+ * Instead, the following registers are treated as global constants:
+ * v14: zero
+ * v15..v18: cosines
+ * v19..v29: permutations
+ * r9: 16
+ * r12: ff_cos_tabs
+ * and the rest are free for local use.
+ */
+
+#include "asm.S"
+
+.text
+
+.macro slwi ra, rb, imm
+ rlwinm \ra, \rb, \imm, 0, 31-\imm
+.endm
+
+.macro addi2 ra, imm // add 32-bit immediate
+.if \imm & 0xffff
+ addi \ra, \ra, \imm at l
+.endif
+.if (\imm+0x8000)>>16
+ addis \ra, \ra, ((\imm+0x8000)>>16) + (\imm&0x800000000000)*0x1fffe
+.endif
+.endm
+
+#if _ARCH_PPC64
+#define PTR .quad
+.macro LOAD_PTR ra, rbase, offset
+ ld \ra,(\offset)*8(\rbase)
+.endm
+.macro STORE_PTR ra, rbase, offset
+ std \ra,(\offset)*8(\rbase)
+.endm
+#else
+#define PTR .int
+.macro LOAD_PTR ra, rbase, offset
+ lwz \ra,(\offset)*4(\rbase)
+.endm
+.macro STORE_PTR ra, rbase, offset
+ stw \ra,(\offset)*4(\rbase)
+.endm
+#endif
+
+.macro FFT4 a0, a1, a2, a3 // in:0-1 out:2-3
+ vperm \a2,\a0,\a1,v20 // vcprm(0,1,s2,s1) // {r0,i0,r3,i2}
+ vperm \a3,\a0,\a1,v21 // vcprm(2,3,s0,s3) // {r1,i1,r2,i3}
+ vaddfp \a0,\a2,\a3 // {t1,t2,t6,t5}
+ vsubfp \a1,\a2,\a3 // {t3,t4,t8,t7}
+ vmrghw \a2,\a0,\a1 // vcprm(0,s0,1,s1) // {t1,t3,t2,t4}
+ vperm \a3,\a0,\a1,v22 // vcprm(2,s3,3,s2) // {t6,t7,t5,t8}
+ vaddfp \a0,\a2,\a3 // {r0,r1,i0,i1}
+ vsubfp \a1,\a2,\a3 // {r2,r3,i2,i3}
+ vperm \a2,\a0,\a1,v23 // vcprm(0,1,s0,s1) // {r0,r1,r2,r3}
+ vperm \a3,\a0,\a1,v24 // vcprm(2,3,s2,s3) // {i0,i1,i2,i3}
+.endm
+
+.macro FFT4x2 a0, a1, b0, b1, a2, a3, b2, b3
+ vperm \a2,\a0,\a1,v20 // vcprm(0,1,s2,s1) // {r0,i0,r3,i2}
+ vperm \a3,\a0,\a1,v21 // vcprm(2,3,s0,s3) // {r1,i1,r2,i3}
+ vperm \b2,\b0,\b1,v20
+ vperm \b3,\b0,\b1,v21
+ vaddfp \a0,\a2,\a3 // {t1,t2,t6,t5}
+ vsubfp \a1,\a2,\a3 // {t3,t4,t8,t7}
+ vaddfp \b0,\b2,\b3
+ vsubfp \b1,\b2,\b3
+ vmrghw \a2,\a0,\a1 // vcprm(0,s0,1,s1) // {t1,t3,t2,t4}
+ vperm \a3,\a0,\a1,v22 // vcprm(2,s3,3,s2) // {t6,t7,t5,t8}
+ vmrghw \b2,\b0,\b1
+ vperm \b3,\b0,\b1,v22
+ vaddfp \a0,\a2,\a3 // {r0,r1,i0,i1}
+ vsubfp \a1,\a2,\a3 // {r2,r3,i2,i3}
+ vaddfp \b0,\b2,\b3
+ vsubfp \b1,\b2,\b3
+ vperm \a2,\a0,\a1,v23 // vcprm(0,1,s0,s1) // {r0,r1,r2,r3}
+ vperm \a3,\a0,\a1,v24 // vcprm(2,3,s2,s3) // {i0,i1,i2,i3}
+ vperm \b2,\b0,\b1,v23
+ vperm \b3,\b0,\b1,v24
+.endm
+
+.macro FFT8 a0, a1, b0, b1, a2, a3, b2, b3, b4 // in,out:a0-b1
+ vmrghw \b2,\b0,\b1 // vcprm(0,s0,1,s1) // {r4,r6,i4,i6}
+ vmrglw \b3,\b0,\b1 // vcprm(2,s2,3,s3) // {r5,r7,i5,i7}
+ vperm \a2,\a0,\a1,v20 // FFT4 ...
+ vperm \a3,\a0,\a1,v21
+ vaddfp \b0,\b2,\b3 // {t1,t3,t2,t4}
+ vsubfp \b1,\b2,\b3 // {r5,r7,i5,i7}
+ vperm \b4,\b1,\b1,v25 // vcprm(2,3,0,1) // {i5,i7,r5,r7}
+ vaddfp \a0,\a2,\a3
+ vsubfp \a1,\a2,\a3
+ vmaddfp \b1,\b1,v17,v14 // * {-1,1,1,-1}/sqrt(2)
+ vmaddfp \b1,\b4,v18,\b1 // * { 1,1,1,1 }/sqrt(2) // {t8,ta,t7,t9}
+ vmrghw \a2,\a0,\a1
+ vperm \a3,\a0,\a1,v22
+ vperm \b2,\b0,\b1,v26 // vcprm(1,2,s3,s0) // {t3,t2,t9,t8}
+ vperm \b3,\b0,\b1,v27 // vcprm(0,3,s2,s1) // {t1,t4,t7,ta}
+ vaddfp \a0,\a2,\a3
+ vsubfp \a1,\a2,\a3
+ vaddfp \b0,\b2,\b3 // {t1,t2,t9,ta}
+ vsubfp \b1,\b2,\b3 // {t6,t5,tc,tb}
+ vperm \a2,\a0,\a1,v23
+ vperm \a3,\a0,\a1,v24
+ vperm \b2,\b0,\b1,v28 // vcprm(0,2,s1,s3) // {t1,t9,t5,tb}
+ vperm \b3,\b0,\b1,v29 // vcprm(1,3,s0,s2) // {t2,ta,t6,tc}
+ vsubfp \b0,\a2,\b2 // {r4,r5,r6,r7}
+ vsubfp \b1,\a3,\b3 // {i4,i5,i6,i7}
+ vaddfp \a0,\a2,\b2 // {r0,r1,r2,r3}
+ vaddfp \a1,\a3,\b3 // {i0,i1,i2,i3}
+.endm
+
+.macro BF d0,d1,s0,s1
+ vsubfp \d1,\s0,\s1
+ vaddfp \d0,\s0,\s1
+.endm
+
+fft4_altivec:
+ lvx v0, 0,r3
+ lvx v1,r9,r3
+ FFT4 v0,v1,v2,v3
+ stvx v2, 0,r3
+ stvx v3,r9,r3
+ blr
+
+fft8_altivec:
+ addi r4,r3,32
+ lvx v0, 0,r3
+ lvx v1,r9,r3
+ lvx v2, 0,r4
+ lvx v3,r9,r4
+ FFT8 v0,v1,v2,v3,v4,v5,v6,v7,v8
+ stvx v0, 0,r3
+ stvx v1,r9,r3
+ stvx v2, 0,r4
+ stvx v3,r9,r4
+ blr
+
+fft16_altivec:
+ addi r5,r3,64
+ addi r6,r3,96
+ addi r4,r3,32
+ lvx v0, 0,r5
+ lvx v1,r9,r5
+ lvx v2, 0,r6
+ lvx v3,r9,r6
+ FFT4x2 v0,v1,v2,v3,v4,v5,v6,v7
+ lvx v0, 0,r3
+ lvx v1,r9,r3
+ lvx v2, 0,r4
+ lvx v3,r9,r4
+ FFT8 v0,v1,v2,v3,v8,v9,v10,v11,v12
+ vmaddfp v8,v4,v15,v14 // r2*wre
+ vmaddfp v9,v5,v15,v14 // i2*wre
+ vmaddfp v10,v6,v15,v14 // r3*wre
+ vmaddfp v11,v7,v15,v14 // i3*wre
+ vmaddfp v8,v5,v16,v8 // i2*wim
+ vnmsubfp v9,v4,v16,v9 // r2*wim
+ vnmsubfp v10,v7,v16,v10 // i3*wim
+ vmaddfp v11,v6,v16,v11 // r3*wim
+ BF v10,v12,v10,v8
+ BF v11,v13,v9,v11
+ BF v0,v4,v0,v10
+ BF v3,v7,v3,v12
+ stvx v0, 0,r3
+ stvx v4, 0,r5
+ stvx v3,r9,r4
+ stvx v7,r9,r6
+ BF v1,v5,v1,v11
+ BF v2,v6,v2,v13
+ stvx v1,r9,r3
+ stvx v5,r9,r5
+ stvx v2, 0,r4
+ stvx v6, 0,r6
+ blr
+
+// void pass(float *z, float *wre, int n)
+.macro PASS interleave, suffix
+fft_pass\suffix\()_altivec:
+ mtctr 5
+ slwi r0,r5,4
+ slwi r7,r5,6 // o2
+ slwi r5,r5,5 // o1
+ add r10,r5,r7 // o3
+ add r0,r4,r0 // wim
+ addi r6,r5,16 // o1+16
+ addi r8,r7,16 // o2+16
+ addi r11,r10,16 // o3+16
+1:
+ lvx v8, 0,r4 // wre
+ lvx v10, 0,r0 // wim
+ sub r0,r0,r9
+ lvx v9, 0,r0
+ vperm v9,v9,v10,v19 // vcprm(s0,3,2,1) => wim[0 .. -3]
+ lvx v4,r3,r7 // r2 = z[o2]
+ lvx v5,r3,r8 // i2 = z[o2+16]
+ lvx v6,r3,r10 // r3 = z[o3]
+ lvx v7,r3,r11 // i3 = z[o3+16]
+ vmaddfp v10,v4,v8,v14 // r2*wre
+ vmaddfp v11,v5,v8,v14 // i2*wre
+ vmaddfp v12,v6,v8,v14 // r3*wre
+ vmaddfp v13,v7,v8,v14 // i3*wre
+ lvx v0, 0,r3 // r0 = z[0]
+ lvx v3,r3,r6 // i1 = z[o1+16]
+ vmaddfp v10,v5,v9,v10 // i2*wim
+ vnmsubfp v11,v4,v9,v11 // r2*wim
+ vnmsubfp v12,v7,v9,v12 // i3*wim
+ vmaddfp v13,v6,v9,v13 // r3*wim
+ lvx v1,r3,r9 // i0 = z[16]
+ lvx v2,r3,r5 // r1 = z[o1]
+ BF v12,v8,v12,v10
+ BF v13,v9,v11,v13
+ BF v0,v4,v0,v12
+ BF v3,v7,v3,v8
+.if !\interleave
+ stvx v0, 0,r3
+ stvx v4,r3,r7
+ stvx v3,r3,r6
+ stvx v7,r3,r11
+.endif
+ BF v1,v5,v1,v13
+ BF v2,v6,v2,v9
+.if !\interleave
+ stvx v1,r3,r9
+ stvx v2,r3,r5
+ stvx v5,r3,r8
+ stvx v6,r3,r10
+.else
+ vmrghw v8,v0,v1
+ vmrglw v9,v0,v1
+ stvx v8, 0,r3
+ stvx v9,r3,r9
+ vmrghw v8,v2,v3
+ vmrglw v9,v2,v3
+ stvx v8,r3,r5
+ stvx v9,r3,r6
+ vmrghw v8,v4,v5
+ vmrglw v9,v4,v5
+ stvx v8,r3,r7
+ stvx v9,r3,r8
+ vmrghw v8,v6,v7
+ vmrglw v9,v6,v7
+ stvx v8,r3,r10
+ stvx v9,r3,r11
+.endif
+ addi r3,r3,32
+ addi r4,r4,16
+ bdnz 1b
+ sub r3,r3,r5
+ blr
+.endm
+
+.macro DECL_FFT suffix, bits, n, n2, n4
+fft\n\suffix\()_altivec:
+ mflr r0
+ STORE_PTR r0,r1,\bits-5
+ bl fft\n2\()_altivec
+ addi2 r3,\n*4
+ bl fft\n4\()_altivec
+ addi2 r3,\n*2
+ bl fft\n4\()_altivec
+ addi2 r3,\n*-6
+ LOAD_PTR r0,r1,\bits-5
+ LOAD_PTR r4,r12,\bits-4
+ mtlr r0
+ li r5,\n/16
+ b fft_pass\suffix\()_altivec
+.endm
+
+.macro DECL_FFTS interleave, suffix
+PASS \interleave, \suffix
+DECL_FFT \suffix,5,32,16,8
+DECL_FFT \suffix,6,64,32,16
+DECL_FFT \suffix,7,128,64,32
+DECL_FFT \suffix,8,256,128,64
+DECL_FFT \suffix,9,512,256,128
+DECL_FFT \suffix,10,1024,512,256
+DECL_FFT \suffix,11,2048,1024,512
+DECL_FFT \suffix,12,4096,2048,1024
+DECL_FFT \suffix,13,8192,4096,2048
+DECL_FFT \suffix,14,16384,8192,4096
+DECL_FFT \suffix,15,32768,16384,8192
+DECL_FFT \suffix,16,65536,32768,16384
+.rodata
+.global ff_fft_dispatch\suffix\()_altivec
+ff_fft_dispatch\suffix\()_altivec:
+PTR fft4_altivec, fft8_altivec, fft16_altivec, fft32\suffix\()_altivec,\
+ fft64\suffix\()_altivec, fft128\suffix\()_altivec, fft256\suffix\()_altivec,\
+ fft512\suffix\()_altivec, fft1024\suffix\()_altivec, fft2048\suffix\()_altivec,\
+ fft4096\suffix\()_altivec, fft8192\suffix\()_altivec, fft16384\suffix\()_altivec,\
+ fft32768\suffix\()_altivec, fft65536\suffix\()_altivec
+.text
+.endm
+
+DECL_FFTS 0
+DECL_FFTS 1, _interleave
diff --git a/libavcodec/ppc/types_altivec.h b/libavcodec/ppc/types_altivec.h
index 2870e83..36b6e1f 100644
--- a/libavcodec/ppc/types_altivec.h
+++ b/libavcodec/ppc/types_altivec.h
@@ -30,6 +30,7 @@
#define vec_s16 vector signed short
#define vec_u32 vector unsigned int
#define vec_s32 vector signed int
+#define vec_f vector float
/***********************************************************************
* Null vector
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