[FFmpeg-devel] [RFC][PATCH 0/3] VC-1 HW Accel field interlaced decoding
h.leppkes at gmail.com
Sun Aug 19 20:34:06 CEST 2012
this patchset adds support for HW accel decoding of VC-1 field interlaced pictures.
It is tested using the DXVA2 hwaccel implementation only, because i do not have a system setup for VA-API (the only other VC1 HW accel).
The first two patches are simple preparations and essentially usable stand-alone without any (known) issues.
Patch 1 disables the full picture header parsing when using a hw accel, because it is not required.
The HW accelerator will perform this parsing itself, and none of the values parsed from the bistream are passed to the HW accelerator. In addition, VC-1 interlaced parsing is known to not be completely tested, so disabling it in a code path where its not required avoids potential bugs.
Patch 2 simplifys handling of the VC-1 BI frames, by keeping the frame type internal to the header parser even when only the basic header parsing is being performed, so the result of the parsing function is consistent on both parsing modes.
Patch 3 then implements field interlaced decoding in the HW accel code path.
In field-interlaced decoding, it is required to pass both fields in seperate calls to the HW accelerator, using the same hardware surface as the decoding target in both calls.
This patch is only tested on DXVA2, but in that setup it is tested quite extensively by me, and my users, as i've been shipping builds with this change to my users for a few month now, and not gotten any complaints.
Because this decoding path is not tested on VA-API, i consider it a RFC at this point, until someone can test it on VA-API and either confirm it works, or we can work together on fixing it for inclusion.
Note that this implementation is for AVHWAccel only, and does not affect the VDPAU decoder at this time (or the software decoder)
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