30 #define HWCAP_RV(letter) (1ul << ((letter) - 'A'))
32 #if HAVE_SYS_HWPROBE_H
33 #include <sys/hwprobe.h>
34 #elif HAVE_ASM_HWPROBE_H
35 #include <asm/hwprobe.h>
36 #include <sys/syscall.h>
39 static int __riscv_hwprobe(
struct riscv_hwprobe *pairs,
size_t pair_count,
43 return syscall(__NR_riscv_hwprobe, pairs, pair_count,
cpu_count,
cpus,
51 #if HAVE_SYS_HWPROBE_H || HAVE_ASM_HWPROBE_H
52 struct riscv_hwprobe pairs[] = {
53 { RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0 },
54 { RISCV_HWPROBE_KEY_IMA_EXT_0, 0 },
55 { RISCV_HWPROBE_KEY_CPUPERF_0, 0 },
59 if (pairs[0].
value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA)
61 #ifdef RISCV_HWPROBE_IMA_V
62 if (pairs[1].
value & RISCV_HWPROBE_IMA_V)
66 #ifdef RISCV_HWPROBE_EXT_ZBB
67 if (pairs[1].
value & RISCV_HWPROBE_EXT_ZBB)
69 #if defined (RISCV_HWPROBE_EXT_ZBA) && defined (RISCV_HWPROBE_EXT_ZBS)
70 if ((pairs[1].
value & RISCV_HWPROBE_EXT_ZBA) &&
71 (pairs[1].
value & RISCV_HWPROBE_EXT_ZBB) &&
72 (pairs[1].
value & RISCV_HWPROBE_EXT_ZBS))
76 #ifdef RISCV_HWPROBE_EXT_ZVBB
77 if (pairs[1].
value & RISCV_HWPROBE_EXT_ZVBB)
80 switch (pairs[2].
value & RISCV_HWPROBE_MISALIGNED_MASK) {
81 case RISCV_HWPROBE_MISALIGNED_FAST:
89 const unsigned long hwcap = getauxval(AT_HWCAP);
91 if (hwcap & HWCAP_RV(
'I'))
93 if (hwcap & HWCAP_RV(
'B'))
97 if (hwcap & HWCAP_RV(
'V'))
110 #if defined (__riscv_b) || \
111 (defined (__riscv_zba) && defined (__riscv_zbb) && defined (__riscv_zbs))
116 #ifdef __riscv_vector
118 #if __riscv_v_elen >= 64
121 #if __riscv_v_elen_fp >= 32
123 #if __riscv_v_elen_fp >= 64