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00022 #include "libavcodec/dsputil.h"
00023
00024 #include "gcc_fixes.h"
00025
00026 #include "util_altivec.h"
00027
00028
00029 #define STEP8(s0, s1, s2, s3, s4, s5, s6, s7, vec_rnd) \
00030 do { \
00031 t0 = vec_sl(vec_add(s0, s4), vec_2); \
00032 t0 = vec_add(vec_sl(t0, vec_1), t0); \
00033 t0 = vec_add(t0, vec_rnd); \
00034 t1 = vec_sl(vec_sub(s0, s4), vec_2); \
00035 t1 = vec_add(vec_sl(t1, vec_1), t1); \
00036 t1 = vec_add(t1, vec_rnd); \
00037 t2 = vec_add(vec_sl(s6, vec_2), vec_sl(s6, vec_1)); \
00038 t2 = vec_add(t2, vec_sl(s2, vec_4)); \
00039 t3 = vec_add(vec_sl(s2, vec_2), vec_sl(s2, vec_1)); \
00040 t3 = vec_sub(t3, vec_sl(s6, vec_4)); \
00041 t4 = vec_add(t0, t2); \
00042 t5 = vec_add(t1, t3); \
00043 t6 = vec_sub(t1, t3); \
00044 t7 = vec_sub(t0, t2); \
00045 \
00046 t0 = vec_sl(vec_add(s1, s3), vec_4); \
00047 t0 = vec_add(t0, vec_sl(s5, vec_3)); \
00048 t0 = vec_add(t0, vec_sl(s7, vec_2)); \
00049 t0 = vec_add(t0, vec_sub(s5, s3)); \
00050 \
00051 t1 = vec_sl(vec_sub(s1, s5), vec_4); \
00052 t1 = vec_sub(t1, vec_sl(s7, vec_3)); \
00053 t1 = vec_sub(t1, vec_sl(s3, vec_2)); \
00054 t1 = vec_sub(t1, vec_add(s1, s7)); \
00055 \
00056 t2 = vec_sl(vec_sub(s7, s3), vec_4); \
00057 t2 = vec_add(t2, vec_sl(s1, vec_3)); \
00058 t2 = vec_add(t2, vec_sl(s5, vec_2)); \
00059 t2 = vec_add(t2, vec_sub(s1, s7)); \
00060 \
00061 t3 = vec_sl(vec_sub(s5, s7), vec_4); \
00062 t3 = vec_sub(t3, vec_sl(s3, vec_3)); \
00063 t3 = vec_add(t3, vec_sl(s1, vec_2)); \
00064 t3 = vec_sub(t3, vec_add(s3, s5)); \
00065 \
00066 s0 = vec_add(t4, t0); \
00067 s1 = vec_add(t5, t1); \
00068 s2 = vec_add(t6, t2); \
00069 s3 = vec_add(t7, t3); \
00070 s4 = vec_sub(t7, t3); \
00071 s5 = vec_sub(t6, t2); \
00072 s6 = vec_sub(t5, t1); \
00073 s7 = vec_sub(t4, t0); \
00074 }while(0)
00075
00076 #define SHIFT_HOR8(s0, s1, s2, s3, s4, s5, s6, s7) \
00077 do { \
00078 s0 = vec_sra(s0, vec_3); \
00079 s1 = vec_sra(s1, vec_3); \
00080 s2 = vec_sra(s2, vec_3); \
00081 s3 = vec_sra(s3, vec_3); \
00082 s4 = vec_sra(s4, vec_3); \
00083 s5 = vec_sra(s5, vec_3); \
00084 s6 = vec_sra(s6, vec_3); \
00085 s7 = vec_sra(s7, vec_3); \
00086 }while(0)
00087
00088 #define SHIFT_VERT8(s0, s1, s2, s3, s4, s5, s6, s7) \
00089 do { \
00090 s0 = vec_sra(s0, vec_7); \
00091 s1 = vec_sra(s1, vec_7); \
00092 s2 = vec_sra(s2, vec_7); \
00093 s3 = vec_sra(s3, vec_7); \
00094 s4 = vec_sra(vec_add(s4, vec_1s), vec_7); \
00095 s5 = vec_sra(vec_add(s5, vec_1s), vec_7); \
00096 s6 = vec_sra(vec_add(s6, vec_1s), vec_7); \
00097 s7 = vec_sra(vec_add(s7, vec_1s), vec_7); \
00098 }while(0)
00099
00100
00101 #define STEP4(s0, s1, s2, s3, vec_rnd) \
00102 do { \
00103 t1 = vec_add(vec_sl(s0, vec_4), s0); \
00104 t1 = vec_add(t1, vec_rnd); \
00105 t2 = vec_add(vec_sl(s2, vec_4), s2); \
00106 t0 = vec_add(t1, t2); \
00107 t1 = vec_sub(t1, t2); \
00108 t3 = vec_sl(vec_sub(s3, s1), vec_1); \
00109 t3 = vec_add(t3, vec_sl(t3, vec_2)); \
00110 t2 = vec_add(t3, vec_sl(s1, vec_5)); \
00111 t3 = vec_add(t3, vec_sl(s3, vec_3)); \
00112 t3 = vec_add(t3, vec_sl(s3, vec_2)); \
00113 s0 = vec_add(t0, t2); \
00114 s1 = vec_sub(t1, t3); \
00115 s2 = vec_add(t1, t3); \
00116 s3 = vec_sub(t0, t2); \
00117 }while (0)
00118
00119 #define SHIFT_HOR4(s0, s1, s2, s3) \
00120 s0 = vec_sra(s0, vec_3); \
00121 s1 = vec_sra(s1, vec_3); \
00122 s2 = vec_sra(s2, vec_3); \
00123 s3 = vec_sra(s3, vec_3);
00124
00125 #define SHIFT_VERT4(s0, s1, s2, s3) \
00126 s0 = vec_sra(s0, vec_7); \
00127 s1 = vec_sra(s1, vec_7); \
00128 s2 = vec_sra(s2, vec_7); \
00129 s3 = vec_sra(s3, vec_7);
00130
00133 static void vc1_inv_trans_8x8_altivec(DCTELEM block[64])
00134 {
00135 vector signed short src0, src1, src2, src3, src4, src5, src6, src7;
00136 vector signed int s0, s1, s2, s3, s4, s5, s6, s7;
00137 vector signed int s8, s9, sA, sB, sC, sD, sE, sF;
00138 vector signed int t0, t1, t2, t3, t4, t5, t6, t7;
00139 const vector signed int vec_64 = vec_sl(vec_splat_s32(4), vec_splat_u32(4));
00140 const vector unsigned int vec_7 = vec_splat_u32(7);
00141 const vector unsigned int vec_4 = vec_splat_u32(4);
00142 const vector signed int vec_4s = vec_splat_s32(4);
00143 const vector unsigned int vec_3 = vec_splat_u32(3);
00144 const vector unsigned int vec_2 = vec_splat_u32(2);
00145 const vector signed int vec_1s = vec_splat_s32(1);
00146 const vector unsigned int vec_1 = vec_splat_u32(1);
00147
00148
00149 src0 = vec_ld( 0, block);
00150 src1 = vec_ld( 16, block);
00151 src2 = vec_ld( 32, block);
00152 src3 = vec_ld( 48, block);
00153 src4 = vec_ld( 64, block);
00154 src5 = vec_ld( 80, block);
00155 src6 = vec_ld( 96, block);
00156 src7 = vec_ld(112, block);
00157
00158 TRANSPOSE8(src0, src1, src2, src3, src4, src5, src6, src7);
00159 s0 = vec_unpackl(src0);
00160 s1 = vec_unpackl(src1);
00161 s2 = vec_unpackl(src2);
00162 s3 = vec_unpackl(src3);
00163 s4 = vec_unpackl(src4);
00164 s5 = vec_unpackl(src5);
00165 s6 = vec_unpackl(src6);
00166 s7 = vec_unpackl(src7);
00167 s8 = vec_unpackh(src0);
00168 s9 = vec_unpackh(src1);
00169 sA = vec_unpackh(src2);
00170 sB = vec_unpackh(src3);
00171 sC = vec_unpackh(src4);
00172 sD = vec_unpackh(src5);
00173 sE = vec_unpackh(src6);
00174 sF = vec_unpackh(src7);
00175 STEP8(s0, s1, s2, s3, s4, s5, s6, s7, vec_4s);
00176 SHIFT_HOR8(s0, s1, s2, s3, s4, s5, s6, s7);
00177 STEP8(s8, s9, sA, sB, sC, sD, sE, sF, vec_4s);
00178 SHIFT_HOR8(s8, s9, sA, sB, sC, sD, sE, sF);
00179 src0 = vec_pack(s8, s0);
00180 src1 = vec_pack(s9, s1);
00181 src2 = vec_pack(sA, s2);
00182 src3 = vec_pack(sB, s3);
00183 src4 = vec_pack(sC, s4);
00184 src5 = vec_pack(sD, s5);
00185 src6 = vec_pack(sE, s6);
00186 src7 = vec_pack(sF, s7);
00187 TRANSPOSE8(src0, src1, src2, src3, src4, src5, src6, src7);
00188
00189 s0 = vec_unpackl(src0);
00190 s1 = vec_unpackl(src1);
00191 s2 = vec_unpackl(src2);
00192 s3 = vec_unpackl(src3);
00193 s4 = vec_unpackl(src4);
00194 s5 = vec_unpackl(src5);
00195 s6 = vec_unpackl(src6);
00196 s7 = vec_unpackl(src7);
00197 s8 = vec_unpackh(src0);
00198 s9 = vec_unpackh(src1);
00199 sA = vec_unpackh(src2);
00200 sB = vec_unpackh(src3);
00201 sC = vec_unpackh(src4);
00202 sD = vec_unpackh(src5);
00203 sE = vec_unpackh(src6);
00204 sF = vec_unpackh(src7);
00205 STEP8(s0, s1, s2, s3, s4, s5, s6, s7, vec_64);
00206 SHIFT_VERT8(s0, s1, s2, s3, s4, s5, s6, s7);
00207 STEP8(s8, s9, sA, sB, sC, sD, sE, sF, vec_64);
00208 SHIFT_VERT8(s8, s9, sA, sB, sC, sD, sE, sF);
00209 src0 = vec_pack(s8, s0);
00210 src1 = vec_pack(s9, s1);
00211 src2 = vec_pack(sA, s2);
00212 src3 = vec_pack(sB, s3);
00213 src4 = vec_pack(sC, s4);
00214 src5 = vec_pack(sD, s5);
00215 src6 = vec_pack(sE, s6);
00216 src7 = vec_pack(sF, s7);
00217
00218 vec_st(src0, 0, block);
00219 vec_st(src1, 16, block);
00220 vec_st(src2, 32, block);
00221 vec_st(src3, 48, block);
00222 vec_st(src4, 64, block);
00223 vec_st(src5, 80, block);
00224 vec_st(src6, 96, block);
00225 vec_st(src7,112, block);
00226 }
00227
00230 static void vc1_inv_trans_8x4_altivec(uint8_t *dest, int stride, DCTELEM *block)
00231 {
00232 vector signed short src0, src1, src2, src3, src4, src5, src6, src7;
00233 vector signed int s0, s1, s2, s3, s4, s5, s6, s7;
00234 vector signed int s8, s9, sA, sB, sC, sD, sE, sF;
00235 vector signed int t0, t1, t2, t3, t4, t5, t6, t7;
00236 const vector signed int vec_64 = vec_sl(vec_splat_s32(4), vec_splat_u32(4));
00237 const vector unsigned int vec_7 = vec_splat_u32(7);
00238 const vector unsigned int vec_5 = vec_splat_u32(5);
00239 const vector unsigned int vec_4 = vec_splat_u32(4);
00240 const vector signed int vec_4s = vec_splat_s32(4);
00241 const vector unsigned int vec_3 = vec_splat_u32(3);
00242 const vector unsigned int vec_2 = vec_splat_u32(2);
00243 const vector unsigned int vec_1 = vec_splat_u32(1);
00244 vector unsigned char tmp;
00245 vector signed short tmp2, tmp3;
00246 vector unsigned char perm0, perm1, p0, p1, p;
00247
00248 src0 = vec_ld( 0, block);
00249 src1 = vec_ld( 16, block);
00250 src2 = vec_ld( 32, block);
00251 src3 = vec_ld( 48, block);
00252 src4 = vec_ld( 64, block);
00253 src5 = vec_ld( 80, block);
00254 src6 = vec_ld( 96, block);
00255 src7 = vec_ld(112, block);
00256
00257 TRANSPOSE8(src0, src1, src2, src3, src4, src5, src6, src7);
00258 s0 = vec_unpackl(src0);
00259 s1 = vec_unpackl(src1);
00260 s2 = vec_unpackl(src2);
00261 s3 = vec_unpackl(src3);
00262 s4 = vec_unpackl(src4);
00263 s5 = vec_unpackl(src5);
00264 s6 = vec_unpackl(src6);
00265 s7 = vec_unpackl(src7);
00266 s8 = vec_unpackh(src0);
00267 s9 = vec_unpackh(src1);
00268 sA = vec_unpackh(src2);
00269 sB = vec_unpackh(src3);
00270 sC = vec_unpackh(src4);
00271 sD = vec_unpackh(src5);
00272 sE = vec_unpackh(src6);
00273 sF = vec_unpackh(src7);
00274 STEP8(s0, s1, s2, s3, s4, s5, s6, s7, vec_4s);
00275 SHIFT_HOR8(s0, s1, s2, s3, s4, s5, s6, s7);
00276 STEP8(s8, s9, sA, sB, sC, sD, sE, sF, vec_4s);
00277 SHIFT_HOR8(s8, s9, sA, sB, sC, sD, sE, sF);
00278 src0 = vec_pack(s8, s0);
00279 src1 = vec_pack(s9, s1);
00280 src2 = vec_pack(sA, s2);
00281 src3 = vec_pack(sB, s3);
00282 src4 = vec_pack(sC, s4);
00283 src5 = vec_pack(sD, s5);
00284 src6 = vec_pack(sE, s6);
00285 src7 = vec_pack(sF, s7);
00286 TRANSPOSE8(src0, src1, src2, src3, src4, src5, src6, src7);
00287
00288 s0 = vec_unpackh(src0);
00289 s1 = vec_unpackh(src1);
00290 s2 = vec_unpackh(src2);
00291 s3 = vec_unpackh(src3);
00292 s8 = vec_unpackl(src0);
00293 s9 = vec_unpackl(src1);
00294 sA = vec_unpackl(src2);
00295 sB = vec_unpackl(src3);
00296 STEP4(s0, s1, s2, s3, vec_64);
00297 SHIFT_VERT4(s0, s1, s2, s3);
00298 STEP4(s8, s9, sA, sB, vec_64);
00299 SHIFT_VERT4(s8, s9, sA, sB);
00300 src0 = vec_pack(s0, s8);
00301 src1 = vec_pack(s1, s9);
00302 src2 = vec_pack(s2, sA);
00303 src3 = vec_pack(s3, sB);
00304
00305 p0 = vec_lvsl (0, dest);
00306 p1 = vec_lvsl (stride, dest);
00307 p = vec_splat_u8 (-1);
00308 perm0 = vec_mergeh (p, p0);
00309 perm1 = vec_mergeh (p, p1);
00310
00311 #define ADD(dest,src,perm) \
00312 \
00313 tmp = vec_ld (0, dest); \
00314 tmp2 = (vector signed short)vec_perm (tmp, vec_splat_u8(0), perm); \
00315 tmp3 = vec_adds (tmp2, src); \
00316 tmp = vec_packsu (tmp3, tmp3); \
00317 vec_ste ((vector unsigned int)tmp, 0, (unsigned int *)dest); \
00318 vec_ste ((vector unsigned int)tmp, 4, (unsigned int *)dest);
00319
00320 ADD (dest, src0, perm0) dest += stride;
00321 ADD (dest, src1, perm1) dest += stride;
00322 ADD (dest, src2, perm0) dest += stride;
00323 ADD (dest, src3, perm1)
00324 }
00325
00326
00327 void vc1dsp_init_altivec(DSPContext* dsp, AVCodecContext *avctx) {
00328 dsp->vc1_inv_trans_8x8 = vc1_inv_trans_8x8_altivec;
00329 dsp->vc1_inv_trans_8x4 = vc1_inv_trans_8x4_altivec;
00330 }