<div dir="auto"><div><div><br><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">пт, 6 сент. 2024 г., 15:02 Andrew Randrianasulu <<a href="mailto:randrianasulu@gmail.com">randrianasulu@gmail.com</a>>:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">On Thu, Sep 5, 2024 at 9:21 AM Andrew Randrianasulu<br>
<<a href="mailto:randrianasulu@gmail.com" target="_blank" rel="noreferrer">randrianasulu@gmail.com</a>> wrote:<br>
><br>
> On Wed, Sep 4, 2024 at 11:27 PM Andrew Randrianasulu<br>
> <<a href="mailto:randrianasulu@gmail.com" target="_blank" rel="noreferrer">randrianasulu@gmail.com</a>> wrote:<br>
> ><br>
> > <a href="https://www.cinelerra-gg.org/bugtracker/view.php?id=665" rel="noreferrer noreferrer" target="_blank">https://www.cinelerra-gg.org/bugtracker/view.php?id=665</a><br>
> ><br>
> > we run into strange problem:<br>
> ><br>
> > if cinelerra-gg uses RGBA-8 format internally we can process yuv444p (full chroma) test sample made with<br>
> ><br>
> > ffmpeg -f lavfi -i yuvtestsrc -frames 1 -color_range 2 /dev/shm/yuv-test.y4m<br>
> ><br>
> > by rendering it to y4m (yuv444p pixel format) and then comparing two files does not show big difference.<br>
> ><br>
> > Yet if we switch our pipeline to yuv (8 bit, 4:4:4) result is totally off (in YUVviewer) for same y4m render.<br>
> ><br>
> > I looked in libswscale and can't see much handling for specifically<br>
> ><br>
> > guest@slax:~/botva/src/mplayer/ffmpeg/libswscale$ grep "AV_PIX_FMT_YUV444P" *.c<br>
> > input.c: case AV_PIX_FMT_YUV444P9LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P10LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P12LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P14LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P16LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P9BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P10BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P12BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P14BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P16BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P9LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P10LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P12LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P14LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P16LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P9BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P10BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P12BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P14BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P16BE:<br>
> > swscale_unscaled.c: if ((srcFormat == AV_PIX_FMT_YUV444P || srcFormat == AV_PIX_FMT_YUVA444P) &&<br>
> > swscale_unscaled.c: if (dstFormat == AV_PIX_FMT_YUV444P &&<br>
> > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat, dstFormat, AV_PIX_FMT_YUV444P9) ||<br>
> > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat, dstFormat, AV_PIX_FMT_YUV444P10) ||<br>
> > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat, dstFormat, AV_PIX_FMT_YUV444P12) ||<br>
> > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat, dstFormat, AV_PIX_FMT_YUV444P14) ||<br>
> > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat, dstFormat, AV_PIX_FMT_YUV444P16))<br>
> > utils.c: [AV_PIX_FMT_YUV444P] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P16LE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P16BE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P9BE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P9LE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P10BE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P10LE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P12BE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P12LE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P14BE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P14LE] = { 1, 1 },<br>
> > utils.c: *format = AV_PIX_FMT_YUV444P;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P: return AV_PIX_FMT_YUV444P;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P9BE: return AV_PIX_FMT_YUV444P9;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P9LE: return AV_PIX_FMT_YUV444P9;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P10BE: return AV_PIX_FMT_YUV444P10;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P10LE: return AV_PIX_FMT_YUV444P10;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P16BE: return AV_PIX_FMT_YUV444P16;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P16LE: return AV_PIX_FMT_YUV444P16;<br>
> ><br>
> > it seems input.c does not deal well with specifically this format? There is no default case in switches ...<br>
> ><br>
> > in swscale_unscaled I also mostly see specific yuv-nv12 wrappers, not yuv444 standalone.<br>
> ><br>
> > util.c is again declares what to do with >8 bpc yuv, mostly.<br>
> ><br>
> > did I miss something important?<br>
> ><br>
> > our ffmpeg mappings live at<br>
> ><br>
> > <a href="https://git.cinelerra-gg.org/git/?p=goodguy/cinelerra.git;a=blob;f=cinelerra-5.1/cinelerra/ffmpeg.C;h=9b8832dd718c94dd8b815edc7eb5c9d732953dd6;hb=HEAD" rel="noreferrer noreferrer" target="_blank">https://git.cinelerra-gg.org/git/?p=goodguy/cinelerra.git;a=blob;f=cinelerra-5.1/cinelerra/ffmpeg.C;h=9b8832dd718c94dd8b815edc7eb5c9d732953dd6;hb=HEAD</a><br>
> ><br>
<br>
so, it seems for our processing we should skip<br>
sws_setColorspaceDetails call if we have both input buffer as yuv and<br>
output pix_fmt is also yuv-something<br>
<br>
Is there any av_* function to see if pixfmt is yuv ? Our mappings<br>
obviously incomplete ....<br></blockquote></div></div></div><div dir="auto"><br></div><div dir="auto">ah, there is something in swscale_internal.h</div><div dir="auto"><br></div><div dir="auto">static av_always_inline int isYUV(enum AVPixelFormat pix_fmt) { const AVPixFmtDescriptor *desc = av_pix_fmt_desc_get(pix_fmt); av_assert0(desc); return !(desc->flags & AV_PIX_FMT_FLAG_RGB) && desc->nb_components >= 2; }<br></div><div dir="auto"><br></div><div dir="auto">looks simple enough to add to our code (gpl2)</div><div dir="auto"><br></div><div dir="auto"><br></div><div dir="auto"><br></div><div dir="auto"><div><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
<br>
> > ps: non-ffmpeg png writer seems to output nearly exactly same png if I set cingg to yuv8 or rgba8 internal processing. So, for same input test file as long as libswscale did its job once on input - pipeline itself does not ruin video, as long as there was no second swscale ? unfortunately we do not have direct yuv writer, so at the end our yuv444 transformed into rgba for saving into tga or png or ppm by our routines.<br>
> ><br>
><br>
> so, I used ffmpeg git up to d9f594209fb1a9c87017034f943dcb311a9d2896<br>
><br>
> make testprog (after ./configure)<br>
><br>
> then I ran<br>
><br>
> guest@slax:/dev/shm/ffmpeg/libswscale/tests$ ./swscale -dst yuv444p > yuv444.log<br>
> cat yuv444.log | grep flags=524296 | grep "96x 96" > 96_yuv444p_flags524296.log<br>
><br>
> from that I see only few conversions show errors > 1?<br>
><br>
> cat 96_yuv444p_flags524296.log<br>
> yuv420p 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD= 0,<br>
> 0, 0, 0<br>
> yuyv422 96x96 -> yuv444p 96x 96 flags=524296 CRC=b060ca43 SSD= 0,<br>
> 4, 2, 0<br>
> rgb24 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,<br>
> 0, 0, 0<br>
> bgr24 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,<br>
> 0, 0, 0<br>
> yuv422p 96x96 -> yuv444p 96x 96 flags=524296 CRC=df1de98f SSD= 0,<br>
> 1, 0, 0<br>
> yuv444p 96x96 -> yuv444p 96x 96 flags=524296 CRC=5073aeb9 SSD= 0,<br>
> 1, 0, 0<br>
> yuv410p 96x96 -> yuv444p 96x 96 flags=524296 CRC=48e60437 SSD= 0,<br>
> 10, 9, 0<br>
> yuv411p 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb8ac6fb SSD= 0,<br>
> 4, 5, 0<br>
> gray 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD= 0,<br>
> 0, 0, 0<br>
> monow 96x96 -> yuv444p 96x 96 flags=524296 CRC=01e024ce SSD=14850,<br>
> 0, 0, 0<br>
> monob 96x96 -> yuv444p 96x 96 flags=524296 CRC=6b366fbe SSD=14769,<br>
> 0, 0, 0<br>
> yuvj420p 96x96 -> yuv444p 96x 96 flags=524296 CRC=f5fc89f5 SSD=<br>
> 0, 0, 0, 0<br>
> yuvj422p 96x96 -> yuv444p 96x 96 flags=524296 CRC=28bcb4f2 SSD=<br>
> 0, 0, 0, 0<br>
> yuvj444p 96x96 -> yuv444p 96x 96 flags=524296 CRC=eb23ece1 SSD=<br>
> 0, 1, 0, 0<br>
> uyvy422 96x96 -> yuv444p 96x 96 flags=524296 CRC=c7973100 SSD= 0,<br>
> 4, 2, 0<br>
> bgr8 96x96 -> yuv444p 96x 96 flags=524296 CRC=2be3ab32 SSD= 92,<br>
> 6, 3, 0<br>
> bgr4_byte 96x96 -> yuv444p 96x 96 flags=524296 CRC=a4f9f904 SSD=<br>
> 1256, 38, 33, 0<br>
> rgb8 96x96 -> yuv444p 96x 96 flags=524296 CRC=2be3ab32 SSD= 92,<br>
> 6, 3, 0<br>
> rgb4_byte 96x96 -> yuv444p 96x 96 flags=524296 CRC=a4f9f904 SSD=<br>
> 1256, 38, 33, 0<br>
> nv12 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD= 0,<br>
> 0, 0, 0<br>
> nv21 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD= 0,<br>
> 0, 0, 0<br>
> argb 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,<br>
> 0, 0, 0<br>
> rgba 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,<br>
> 0, 0, 0<br>
> abgr 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,<br>
> 0, 0, 0<br>
> bgra 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,<br>
> 0, 0, 0<br>
> gray16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=2e43f8fd SSD=<br>
> 0, 0, 0, 0<br>
> gray16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=2e43f8fd SSD=<br>
> 0, 0, 0, 0<br>
> yuv440p 96x96 -> yuv444p 96x 96 flags=524296 CRC=244073c9 SSD= 0,<br>
> 0, 0, 0<br>
> yuvj440p 96x96 -> yuv444p 96x 96 flags=524296 CRC=228c0b93 SSD=<br>
> 0, 0, 0, 0<br>
> yuva420p 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD=<br>
> 0, 0, 0, 0<br>
> rgb48be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,<br>
> 0, 0, 0<br>
> rgb48le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,<br>
> 0, 0, 0<br>
> rgb565be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c3d3be78 SSD=<br>
> 2, 4, 3, 0<br>
> rgb565le 96x96 -> yuv444p 96x 96 flags=524296 CRC=12edcd77 SSD=<br>
> 3, 0, 0, 0<br>
> rgb555be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9a8ede80 SSD=<br>
> 4, 4, 3, 0<br>
> rgb555le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da784ee1 SSD=<br>
> 4, 0, 0, 0<br>
> bgr565be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c3d3be78 SSD=<br>
> 2, 4, 3, 0<br>
> bgr565le 96x96 -> yuv444p 96x 96 flags=524296 CRC=0496c046 SSD=<br>
> 2, 0, 0, 0<br>
> bgr555be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9a8ede80 SSD=<br>
> 4, 4, 3, 0<br>
> bgr555le 96x96 -> yuv444p 96x 96 flags=524296 CRC=21eaab36 SSD=<br>
> 4, 0, 0, 0<br>
> yuv420p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv444p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=<br>
> 0, 1, 1, 0<br>
> yuv444p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=<br>
> 0, 1, 1, 0<br>
> rgb444le 96x96 -> yuv444p 96x 96 flags=524296 CRC=b651f543 SSD=<br>
> 28, 1, 1, 0<br>
> rgb444be 96x96 -> yuv444p 96x 96 flags=524296 CRC=eecdc127 SSD=<br>
> 11, 4, 3, 0<br>
> bgr444le 96x96 -> yuv444p 96x 96 flags=524296 CRC=b651f543 SSD=<br>
> 28, 1, 1, 0<br>
> bgr444be 96x96 -> yuv444p 96x 96 flags=524296 CRC=eecdc127 SSD=<br>
> 11, 4, 3, 0<br>
> ya8 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD= 0,<br>
> 0, 0, 0<br>
> bgr48be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,<br>
> 0, 0, 0<br>
> bgr48le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,<br>
> 0, 0, 0<br>
> yuv420p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv444p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=<br>
> 0, 1, 0, 0<br>
> yuv444p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=<br>
> 0, 1, 0, 0<br>
> yuv444p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=<br>
> 0, 1, 0, 0<br>
> yuv444p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=<br>
> 0, 1, 0, 0<br>
> yuv422p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=<br>
> 0, 0, 0, 0<br>
> gbrp 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,<br>
> 0, 0, 0<br>
> gbrp9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=333371d5 SSD= 0,<br>
> 1, 0, 0<br>
> gbrp9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=333371d5 SSD= 0,<br>
> 1, 0, 0<br>
> gbrp10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=<br>
> 0, 1, 0, 0<br>
> yuva422p 96x96 -> yuv444p 96x 96 flags=524296 CRC=df1de98f SSD=<br>
> 0, 1, 0, 0<br>
> yuva444p 96x96 -> yuv444p 96x 96 flags=524296 CRC=5073aeb9 SSD=<br>
> 0, 1, 0, 0<br>
> yuva420p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuva420p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=<br>
> 0, 0, 0, 0<br>
> yuva444p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=<br>
> 0, 1, 0, 0<br>
> yuva444p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=<br>
> 0, 1, 0, 0<br>
> yuva420p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuva420p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuva444p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=<br>
> 0, 1, 0, 0<br>
> yuva444p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=<br>
> 0, 1, 0, 0<br>
> yuva420p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuva420p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuva444p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=<br>
> 0, 1, 1, 0<br>
> yuva444p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=<br>
> 0, 1, 1, 0<br>
> xyz12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=44ea94ba SSD= 1,<br>
> 0, 0, 0<br>
> xyz12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=44ea94ba SSD= 1,<br>
> 0, 0, 0<br>
> nv16 96x96 -> yuv444p 96x 96 flags=524296 CRC=df1de98f SSD= 0,<br>
> 1, 0, 0<br>
> rgba64be 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=<br>
> 0, 3, 2, 0<br>
> rgba64le 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=<br>
> 0, 3, 2, 0<br>
> bgra64be 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=<br>
> 0, 3, 2, 0<br>
> bgra64le 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=<br>
> 0, 3, 2, 0<br>
> yvyu422 96x96 -> yuv444p 96x 96 flags=524296 CRC=c7973100 SSD= 0,<br>
> 4, 2, 0<br>
> ya16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=5c8c4e0f SSD= 0,<br>
> 0, 0, 0<br>
> ya16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=5c8c4e0f SSD= 0,<br>
> 0, 0, 0<br>
> gbrap 96x96 -> yuv444p 96x 96 flags=524296 CRC=4d1e6edb SSD= 0,<br>
> 1, 0, 0<br>
> gbrap16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=<br>
> 0, 1, 0, 0<br>
> gbrap16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=<br>
> 0, 1, 0, 0<br>
> 0rgb 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,<br>
> 0, 0, 0<br>
> rgb0 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,<br>
> 0, 0, 0<br>
> 0bgr 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,<br>
> 0, 0, 0<br>
> bgr0 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,<br>
> 0, 0, 0<br>
> yuv420p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv444p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=<br>
> 0, 1, 0, 0<br>
> yuv444p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=<br>
> 0, 1, 0, 0<br>
> yuv444p14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=<br>
> 0, 1, 0, 0<br>
> yuv444p14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=<br>
> 0, 1, 0, 0<br>
> yuvj411p 96x96 -> yuv444p 96x 96 flags=524296 CRC=fc11b7a8 SSD=<br>
> 0, 4, 5, 0<br>
> yuv440p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=<br>
> 0, 0, 0, 0<br>
> yuv440p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=<br>
> 0, 0, 0, 0<br>
> yuv440p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=<br>
> 0, 0, 0, 0<br>
> yuv440p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=<br>
> 0, 0, 0, 0<br>
> ayuv64le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD=<br>
> 0, 1, 0, 0<br>
> p010le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e396057d SSD= 0,<br>
> 0, 0, 0<br>
> p010be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,<br>
> 0, 0, 0<br>
> gbrap12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=<br>
> 0, 1, 0, 0<br>
> gbrap12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=<br>
> 0, 1, 0, 0<br>
> gbrap10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=<br>
> 0, 1, 0, 0<br>
> gbrap10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=<br>
> 0, 1, 0, 0<br>
> gray12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=d9a892ec SSD=<br>
> 0, 958, 667, 0<br>
> gray12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=d9a892ec SSD=<br>
> 0, 958, 667, 0<br>
> gray10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=a29dc987 SSD=<br>
> 0, 958, 667, 0<br>
> gray10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=a29dc987 SSD=<br>
> 0, 958, 667, 0<br>
> p016le 96x96 -> yuv444p 96x 96 flags=524296 CRC=123d3ef9 SSD= 0,<br>
> 1, 0, 0<br>
> p016be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,<br>
> 0, 0, 0<br>
> gray9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=90e6a330 SSD= 0,<br>
> 958, 667, 0<br>
> gray9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=90e6a330 SSD= 0,<br>
> 958, 667, 0<br>
> gbrpf32be 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=<br>
> 0, 1, 0, 0<br>
> gbrpf32le 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=<br>
> 0, 1, 0, 0<br>
> gbrapf32be 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=<br>
> 0, 1, 0, 0<br>
> gbrapf32le 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=<br>
> 0, 1, 0, 0<br>
> gray14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=<br>
> 0, 958, 667, 0<br>
> gray14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=<br>
> 0, 958, 667, 0<br>
> grayf32be 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=<br>
> 0, 958, 667, 0<br>
> grayf32le 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=<br>
> 0, 958, 667, 0<br>
> yuva422p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuva444p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=<br>
> 0, 1, 0, 0<br>
> yuva444p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=<br>
> 0, 1, 0, 0<br>
> nv24 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,<br>
> 1, 0, 0<br>
> nv42 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,<br>
> 1, 0, 0<br>
> y210le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> x2rgb10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=28220704 SSD=<br>
> 1, 3, 2, 0<br>
> x2bgr10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=28220704 SSD=<br>
> 1, 3, 2, 0<br>
> p210be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> p210le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> p410be 96x96 -> yuv444p 96x 96 flags=524296 CRC=15ee96d0 SSD= 0,<br>
> 1, 0, 0<br>
> p410le 96x96 -> yuv444p 96x 96 flags=524296 CRC=15ee96d0 SSD= 0,<br>
> 1, 0, 0<br>
> p216be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> p216le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> p416be 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,<br>
> 1, 0, 0<br>
> p416le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,<br>
> 1, 0, 0<br>
> vuya 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,<br>
> 1, 0, 0<br>
> vuyx 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,<br>
> 1, 0, 0<br>
> p012le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,<br>
> 0, 0, 0<br>
> p012be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,<br>
> 0, 0, 0<br>
> y212le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> xv30le 96x96 -> yuv444p 96x 96 flags=524296 CRC=15ee96d0 SSD= 0,<br>
> 1, 0, 0<br>
> xv36le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,<br>
> 1, 0, 0<br>
> p212be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> p212le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> p412be 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,<br>
> 1, 0, 0<br>
><br>
><br>
> p412le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,<br>
> 1, 0, 0<br>
> gbrap14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=<br>
> 0, 1, 0, 0<br>
> gbrap14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=<br>
> 0, 1, 0, 0<br>
><br>
> =====<br>
><br>
> grayf32le<br>
> gray12be<br>
> yvyu422<br>
> bgra64le<br>
> rgb444le<br>
> bgr555be<br>
> yuv410p<br>
> yuv411p<br>
> yuyv422<br>
><br>
> This is on<br>
><br>
> LANG=C lscpu<br>
> Architecture: x86_64<br>
> CPU op-mode(s): 32-bit, 64-bit<br>
> Address sizes: 48 bits physical, 48 bits virtual<br>
> Byte Order: Little Endian<br>
> CPU(s): 4<br>
> On-line CPU(s) list: 0-3<br>
> Vendor ID: AuthenticAMD<br>
> Model name: AMD FX(tm)-4300 Quad-Core Processor<br>
> CPU family: 21<br>
> Model: 2<br>
> Thread(s) per core: 2<br>
> Core(s) per socket: 2<br>
> Socket(s): 1<br>
> Stepping: 0<br>
> Frequency boost: enabled<br>
> CPU max MHz: 3800.0000<br>
> CPU min MHz: 1400.0000<br>
> BogoMIPS: 7583.64<br>
> Flags: fpu vme de pse tsc msr pae mce cx8 apic sep<br>
> mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht sys<br>
> call nx mmxext fxsr_opt pdpe1gb rdtscp lm<br>
> constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperf<br>
> mperf pni pclmulqdq monitor ssse3 fma cx16<br>
> sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy sv<br>
> m extapic cr8_legacy abm sse4a misalignsse<br>
> 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr<br>
> tbm topoext perfctr_core perfctr_nb cpb<br>
> hw_pstate ssbd vmmcall bmi1 arat npt lbrv svm_lock nrip_save ts<br>
> c_scale vmcb_clean flushbyasid decodeassists<br>
> pausefilter pfthreshold<br>
><br>
> on Slackware 15.0 i586 with 64-bit kernel.<br>
</blockquote></div></div><br><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">пт, 6 сент. 2024 г., 15:02 Andrew Randrianasulu <<a href="mailto:randrianasulu@gmail.com">randrianasulu@gmail.com</a>>:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">On Thu, Sep 5, 2024 at 9:21 AM Andrew Randrianasulu<br>
<<a href="mailto:randrianasulu@gmail.com" target="_blank" rel="noreferrer">randrianasulu@gmail.com</a>> wrote:<br>
><br>
> On Wed, Sep 4, 2024 at 11:27 PM Andrew Randrianasulu<br>
> <<a href="mailto:randrianasulu@gmail.com" target="_blank" rel="noreferrer">randrianasulu@gmail.com</a>> wrote:<br>
> ><br>
> > <a href="https://www.cinelerra-gg.org/bugtracker/view.php?id=665" rel="noreferrer noreferrer" target="_blank">https://www.cinelerra-gg.org/bugtracker/view.php?id=665</a><br>
> ><br>
> > we run into strange problem:<br>
> ><br>
> > if cinelerra-gg uses RGBA-8 format internally we can process yuv444p (full chroma) test sample made with<br>
> ><br>
> > ffmpeg -f lavfi -i yuvtestsrc -frames 1 -color_range 2 /dev/shm/yuv-test.y4m<br>
> ><br>
> > by rendering it to y4m (yuv444p pixel format) and then comparing two files does not show big difference.<br>
> ><br>
> > Yet if we switch our pipeline to yuv (8 bit, 4:4:4) result is totally off (in YUVviewer) for same y4m render.<br>
> ><br>
> > I looked in libswscale and can't see much handling for specifically<br>
> ><br>
> > guest@slax:~/botva/src/mplayer/ffmpeg/libswscale$ grep "AV_PIX_FMT_YUV444P" *.c<br>
> > input.c: case AV_PIX_FMT_YUV444P9LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P10LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P12LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P14LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P16LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P9BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P10BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P12BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P14BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P16BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P9LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P10LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P12LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P14LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P16LE:<br>
> > input.c: case AV_PIX_FMT_YUV444P9BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P10BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P12BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P14BE:<br>
> > input.c: case AV_PIX_FMT_YUV444P16BE:<br>
> > swscale_unscaled.c: if ((srcFormat == AV_PIX_FMT_YUV444P || srcFormat == AV_PIX_FMT_YUVA444P) &&<br>
> > swscale_unscaled.c: if (dstFormat == AV_PIX_FMT_YUV444P &&<br>
> > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat, dstFormat, AV_PIX_FMT_YUV444P9) ||<br>
> > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat, dstFormat, AV_PIX_FMT_YUV444P10) ||<br>
> > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat, dstFormat, AV_PIX_FMT_YUV444P12) ||<br>
> > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat, dstFormat, AV_PIX_FMT_YUV444P14) ||<br>
> > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat, dstFormat, AV_PIX_FMT_YUV444P16))<br>
> > utils.c: [AV_PIX_FMT_YUV444P] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P16LE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P16BE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P9BE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P9LE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P10BE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P10LE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P12BE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P12LE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P14BE] = { 1, 1 },<br>
> > utils.c: [AV_PIX_FMT_YUV444P14LE] = { 1, 1 },<br>
> > utils.c: *format = AV_PIX_FMT_YUV444P;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P: return AV_PIX_FMT_YUV444P;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P9BE: return AV_PIX_FMT_YUV444P9;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P9LE: return AV_PIX_FMT_YUV444P9;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P10BE: return AV_PIX_FMT_YUV444P10;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P10LE: return AV_PIX_FMT_YUV444P10;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P16BE: return AV_PIX_FMT_YUV444P16;<br>
> > utils.c: case AV_PIX_FMT_YUVA444P16LE: return AV_PIX_FMT_YUV444P16;<br>
> ><br>
> > it seems input.c does not deal well with specifically this format? There is no default case in switches ...<br>
> ><br>
> > in swscale_unscaled I also mostly see specific yuv-nv12 wrappers, not yuv444 standalone.<br>
> ><br>
> > util.c is again declares what to do with >8 bpc yuv, mostly.<br>
> ><br>
> > did I miss something important?<br>
> ><br>
> > our ffmpeg mappings live at<br>
> ><br>
> > <a href="https://git.cinelerra-gg.org/git/?p=goodguy/cinelerra.git;a=blob;f=cinelerra-5.1/cinelerra/ffmpeg.C;h=9b8832dd718c94dd8b815edc7eb5c9d732953dd6;hb=HEAD" rel="noreferrer noreferrer" target="_blank">https://git.cinelerra-gg.org/git/?p=goodguy/cinelerra.git;a=blob;f=cinelerra-5.1/cinelerra/ffmpeg.C;h=9b8832dd718c94dd8b815edc7eb5c9d732953dd6;hb=HEAD</a><br>
> ><br>
<br>
so, it seems for our processing we should skip<br>
sws_setColorspaceDetails call if we have both input buffer as yuv and<br>
output pix_fmt is also yuv-something<br>
<br>
Is there any av_* function to see if pixfmt is yuv ? Our mappings<br>
obviously incomplete ....<br>
<br>
<br>
> > ps: non-ffmpeg png writer seems to output nearly exactly same png if I set cingg to yuv8 or rgba8 internal processing. So, for same input test file as long as libswscale did its job once on input - pipeline itself does not ruin video, as long as there was no second swscale ? unfortunately we do not have direct yuv writer, so at the end our yuv444 transformed into rgba for saving into tga or png or ppm by our routines.<br>
> ><br>
><br>
> so, I used ffmpeg git up to d9f594209fb1a9c87017034f943dcb311a9d2896<br>
><br>
> make testprog (after ./configure)<br>
><br>
> then I ran<br>
><br>
> guest@slax:/dev/shm/ffmpeg/libswscale/tests$ ./swscale -dst yuv444p > yuv444.log<br>
> cat yuv444.log | grep flags=524296 | grep "96x 96" > 96_yuv444p_flags524296.log<br>
><br>
> from that I see only few conversions show errors > 1?<br>
><br>
> cat 96_yuv444p_flags524296.log<br>
> yuv420p 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD= 0,<br>
> 0, 0, 0<br>
> yuyv422 96x96 -> yuv444p 96x 96 flags=524296 CRC=b060ca43 SSD= 0,<br>
> 4, 2, 0<br>
> rgb24 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,<br>
> 0, 0, 0<br>
> bgr24 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,<br>
> 0, 0, 0<br>
> yuv422p 96x96 -> yuv444p 96x 96 flags=524296 CRC=df1de98f SSD= 0,<br>
> 1, 0, 0<br>
> yuv444p 96x96 -> yuv444p 96x 96 flags=524296 CRC=5073aeb9 SSD= 0,<br>
> 1, 0, 0<br>
> yuv410p 96x96 -> yuv444p 96x 96 flags=524296 CRC=48e60437 SSD= 0,<br>
> 10, 9, 0<br>
> yuv411p 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb8ac6fb SSD= 0,<br>
> 4, 5, 0<br>
> gray 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD= 0,<br>
> 0, 0, 0<br>
> monow 96x96 -> yuv444p 96x 96 flags=524296 CRC=01e024ce SSD=14850,<br>
> 0, 0, 0<br>
> monob 96x96 -> yuv444p 96x 96 flags=524296 CRC=6b366fbe SSD=14769,<br>
> 0, 0, 0<br>
> yuvj420p 96x96 -> yuv444p 96x 96 flags=524296 CRC=f5fc89f5 SSD=<br>
> 0, 0, 0, 0<br>
> yuvj422p 96x96 -> yuv444p 96x 96 flags=524296 CRC=28bcb4f2 SSD=<br>
> 0, 0, 0, 0<br>
> yuvj444p 96x96 -> yuv444p 96x 96 flags=524296 CRC=eb23ece1 SSD=<br>
> 0, 1, 0, 0<br>
> uyvy422 96x96 -> yuv444p 96x 96 flags=524296 CRC=c7973100 SSD= 0,<br>
> 4, 2, 0<br>
> bgr8 96x96 -> yuv444p 96x 96 flags=524296 CRC=2be3ab32 SSD= 92,<br>
> 6, 3, 0<br>
> bgr4_byte 96x96 -> yuv444p 96x 96 flags=524296 CRC=a4f9f904 SSD=<br>
> 1256, 38, 33, 0<br>
> rgb8 96x96 -> yuv444p 96x 96 flags=524296 CRC=2be3ab32 SSD= 92,<br>
> 6, 3, 0<br>
> rgb4_byte 96x96 -> yuv444p 96x 96 flags=524296 CRC=a4f9f904 SSD=<br>
> 1256, 38, 33, 0<br>
> nv12 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD= 0,<br>
> 0, 0, 0<br>
> nv21 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD= 0,<br>
> 0, 0, 0<br>
> argb 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,<br>
> 0, 0, 0<br>
> rgba 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,<br>
> 0, 0, 0<br>
> abgr 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,<br>
> 0, 0, 0<br>
> bgra 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,<br>
> 0, 0, 0<br>
> gray16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=2e43f8fd SSD=<br>
> 0, 0, 0, 0<br>
> gray16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=2e43f8fd SSD=<br>
> 0, 0, 0, 0<br>
> yuv440p 96x96 -> yuv444p 96x 96 flags=524296 CRC=244073c9 SSD= 0,<br>
> 0, 0, 0<br>
> yuvj440p 96x96 -> yuv444p 96x 96 flags=524296 CRC=228c0b93 SSD=<br>
> 0, 0, 0, 0<br>
> yuva420p 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD=<br>
> 0, 0, 0, 0<br>
> rgb48be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,<br>
> 0, 0, 0<br>
> rgb48le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,<br>
> 0, 0, 0<br>
> rgb565be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c3d3be78 SSD=<br>
> 2, 4, 3, 0<br>
> rgb565le 96x96 -> yuv444p 96x 96 flags=524296 CRC=12edcd77 SSD=<br>
> 3, 0, 0, 0<br>
> rgb555be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9a8ede80 SSD=<br>
> 4, 4, 3, 0<br>
> rgb555le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da784ee1 SSD=<br>
> 4, 0, 0, 0<br>
> bgr565be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c3d3be78 SSD=<br>
> 2, 4, 3, 0<br>
> bgr565le 96x96 -> yuv444p 96x 96 flags=524296 CRC=0496c046 SSD=<br>
> 2, 0, 0, 0<br>
> bgr555be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9a8ede80 SSD=<br>
> 4, 4, 3, 0<br>
> bgr555le 96x96 -> yuv444p 96x 96 flags=524296 CRC=21eaab36 SSD=<br>
> 4, 0, 0, 0<br>
> yuv420p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv444p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=<br>
> 0, 1, 1, 0<br>
> yuv444p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=<br>
> 0, 1, 1, 0<br>
> rgb444le 96x96 -> yuv444p 96x 96 flags=524296 CRC=b651f543 SSD=<br>
> 28, 1, 1, 0<br>
> rgb444be 96x96 -> yuv444p 96x 96 flags=524296 CRC=eecdc127 SSD=<br>
> 11, 4, 3, 0<br>
> bgr444le 96x96 -> yuv444p 96x 96 flags=524296 CRC=b651f543 SSD=<br>
> 28, 1, 1, 0<br>
> bgr444be 96x96 -> yuv444p 96x 96 flags=524296 CRC=eecdc127 SSD=<br>
> 11, 4, 3, 0<br>
> ya8 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD= 0,<br>
> 0, 0, 0<br>
> bgr48be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,<br>
> 0, 0, 0<br>
> bgr48le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,<br>
> 0, 0, 0<br>
> yuv420p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv444p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=<br>
> 0, 1, 0, 0<br>
> yuv444p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=<br>
> 0, 1, 0, 0<br>
> yuv444p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=<br>
> 0, 1, 0, 0<br>
> yuv444p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=<br>
> 0, 1, 0, 0<br>
> yuv422p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=<br>
> 0, 0, 0, 0<br>
> gbrp 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,<br>
> 0, 0, 0<br>
> gbrp9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=333371d5 SSD= 0,<br>
> 1, 0, 0<br>
> gbrp9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=333371d5 SSD= 0,<br>
> 1, 0, 0<br>
> gbrp10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=<br>
> 0, 1, 0, 0<br>
> yuva422p 96x96 -> yuv444p 96x 96 flags=524296 CRC=df1de98f SSD=<br>
> 0, 1, 0, 0<br>
> yuva444p 96x96 -> yuv444p 96x 96 flags=524296 CRC=5073aeb9 SSD=<br>
> 0, 1, 0, 0<br>
> yuva420p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuva420p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=<br>
> 0, 0, 0, 0<br>
> yuva444p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=<br>
> 0, 1, 0, 0<br>
> yuva444p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=<br>
> 0, 1, 0, 0<br>
> yuva420p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuva420p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuva444p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=<br>
> 0, 1, 0, 0<br>
> yuva444p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=<br>
> 0, 1, 0, 0<br>
> yuva420p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuva420p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuva444p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=<br>
> 0, 1, 1, 0<br>
> yuva444p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=<br>
> 0, 1, 1, 0<br>
> xyz12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=44ea94ba SSD= 1,<br>
> 0, 0, 0<br>
> xyz12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=44ea94ba SSD= 1,<br>
> 0, 0, 0<br>
> nv16 96x96 -> yuv444p 96x 96 flags=524296 CRC=df1de98f SSD= 0,<br>
> 1, 0, 0<br>
> rgba64be 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=<br>
> 0, 3, 2, 0<br>
> rgba64le 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=<br>
> 0, 3, 2, 0<br>
> bgra64be 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=<br>
> 0, 3, 2, 0<br>
> bgra64le 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=<br>
> 0, 3, 2, 0<br>
> yvyu422 96x96 -> yuv444p 96x 96 flags=524296 CRC=c7973100 SSD= 0,<br>
> 4, 2, 0<br>
> ya16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=5c8c4e0f SSD= 0,<br>
> 0, 0, 0<br>
> ya16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=5c8c4e0f SSD= 0,<br>
> 0, 0, 0<br>
> gbrap 96x96 -> yuv444p 96x 96 flags=524296 CRC=4d1e6edb SSD= 0,<br>
> 1, 0, 0<br>
> gbrap16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=<br>
> 0, 1, 0, 0<br>
> gbrap16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=<br>
> 0, 1, 0, 0<br>
> 0rgb 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,<br>
> 0, 0, 0<br>
> rgb0 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,<br>
> 0, 0, 0<br>
> 0bgr 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,<br>
> 0, 0, 0<br>
> bgr0 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,<br>
> 0, 0, 0<br>
> yuv420p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv420p14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv422p14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuv444p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=<br>
> 0, 1, 0, 0<br>
> yuv444p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=<br>
> 0, 1, 0, 0<br>
> yuv444p14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=<br>
> 0, 1, 0, 0<br>
> yuv444p14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=<br>
> 0, 1, 0, 0<br>
> gbrp14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=<br>
> 0, 1, 0, 0<br>
> yuvj411p 96x96 -> yuv444p 96x 96 flags=524296 CRC=fc11b7a8 SSD=<br>
> 0, 4, 5, 0<br>
> yuv440p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=<br>
> 0, 0, 0, 0<br>
> yuv440p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=<br>
> 0, 0, 0, 0<br>
> yuv440p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=<br>
> 0, 0, 0, 0<br>
> yuv440p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=<br>
> 0, 0, 0, 0<br>
> ayuv64le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD=<br>
> 0, 1, 0, 0<br>
> p010le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e396057d SSD= 0,<br>
> 0, 0, 0<br>
> p010be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,<br>
> 0, 0, 0<br>
> gbrap12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=<br>
> 0, 1, 0, 0<br>
> gbrap12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=<br>
> 0, 1, 0, 0<br>
> gbrap10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=<br>
> 0, 1, 0, 0<br>
> gbrap10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=<br>
> 0, 1, 0, 0<br>
> gray12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=d9a892ec SSD=<br>
> 0, 958, 667, 0<br>
> gray12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=d9a892ec SSD=<br>
> 0, 958, 667, 0<br>
> gray10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=a29dc987 SSD=<br>
> 0, 958, 667, 0<br>
> gray10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=a29dc987 SSD=<br>
> 0, 958, 667, 0<br>
> p016le 96x96 -> yuv444p 96x 96 flags=524296 CRC=123d3ef9 SSD= 0,<br>
> 1, 0, 0<br>
> p016be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,<br>
> 0, 0, 0<br>
> gray9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=90e6a330 SSD= 0,<br>
> 958, 667, 0<br>
> gray9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=90e6a330 SSD= 0,<br>
> 958, 667, 0<br>
> gbrpf32be 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=<br>
> 0, 1, 0, 0<br>
> gbrpf32le 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=<br>
> 0, 1, 0, 0<br>
> gbrapf32be 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=<br>
> 0, 1, 0, 0<br>
> gbrapf32le 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=<br>
> 0, 1, 0, 0<br>
> gray14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=<br>
> 0, 958, 667, 0<br>
> gray14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=<br>
> 0, 958, 667, 0<br>
> grayf32be 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=<br>
> 0, 958, 667, 0<br>
> grayf32le 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=<br>
> 0, 958, 667, 0<br>
> yuva422p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuva422p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=<br>
> 0, 0, 0, 0<br>
> yuva444p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=<br>
> 0, 1, 0, 0<br>
> yuva444p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=<br>
> 0, 1, 0, 0<br>
> nv24 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,<br>
> 1, 0, 0<br>
> nv42 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,<br>
> 1, 0, 0<br>
> y210le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> x2rgb10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=28220704 SSD=<br>
> 1, 3, 2, 0<br>
> x2bgr10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=28220704 SSD=<br>
> 1, 3, 2, 0<br>
> p210be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> p210le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> p410be 96x96 -> yuv444p 96x 96 flags=524296 CRC=15ee96d0 SSD= 0,<br>
> 1, 0, 0<br>
> p410le 96x96 -> yuv444p 96x 96 flags=524296 CRC=15ee96d0 SSD= 0,<br>
> 1, 0, 0<br>
> p216be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> p216le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> p416be 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,<br>
> 1, 0, 0<br>
> p416le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,<br>
> 1, 0, 0<br>
> vuya 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,<br>
> 1, 0, 0<br>
> vuyx 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,<br>
> 1, 0, 0<br>
> p012le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,<br>
> 0, 0, 0<br>
> p012be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,<br>
> 0, 0, 0<br>
> y212le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> xv30le 96x96 -> yuv444p 96x 96 flags=524296 CRC=15ee96d0 SSD= 0,<br>
> 1, 0, 0<br>
> xv36le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,<br>
> 1, 0, 0<br>
> p212be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> p212le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,<br>
> 0, 0, 0<br>
> p412be 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,<br>
> 1, 0, 0<br>
><br>
><br>
> p412le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,<br>
> 1, 0, 0<br>
> gbrap14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=<br>
> 0, 1, 0, 0<br>
> gbrap14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=<br>
> 0, 1, 0, 0<br>
><br>
> =====<br>
><br>
> grayf32le<br>
> gray12be<br>
> yvyu422<br>
> bgra64le<br>
> rgb444le<br>
> bgr555be<br>
> yuv410p<br>
> yuv411p<br>
> yuyv422<br>
><br>
> This is on<br>
><br>
> LANG=C lscpu<br>
> Architecture: x86_64<br>
> CPU op-mode(s): 32-bit, 64-bit<br>
> Address sizes: 48 bits physical, 48 bits virtual<br>
> Byte Order: Little Endian<br>
> CPU(s): 4<br>
> On-line CPU(s) list: 0-3<br>
> Vendor ID: AuthenticAMD<br>
> Model name: AMD FX(tm)-4300 Quad-Core Processor<br>
> CPU family: 21<br>
> Model: 2<br>
> Thread(s) per core: 2<br>
> Core(s) per socket: 2<br>
> Socket(s): 1<br>
> Stepping: 0<br>
> Frequency boost: enabled<br>
> CPU max MHz: 3800.0000<br>
> CPU min MHz: 1400.0000<br>
> BogoMIPS: 7583.64<br>
> Flags: fpu vme de pse tsc msr pae mce cx8 apic sep<br>
> mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht sys<br>
> call nx mmxext fxsr_opt pdpe1gb rdtscp lm<br>
> constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperf<br>
> mperf pni pclmulqdq monitor ssse3 fma cx16<br>
> sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy sv<br>
> m extapic cr8_legacy abm sse4a misalignsse<br>
> 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr<br>
> tbm topoext perfctr_core perfctr_nb cpb<br>
> hw_pstate ssbd vmmcall bmi1 arat npt lbrv svm_lock nrip_save ts<br>
> c_scale vmcb_clean flushbyasid decodeassists<br>
> pausefilter pfthreshold<br>
><br>
> on Slackware 15.0 i586 with 64-bit kernel.<br>
</blockquote></div></div></div>