[Ffmpeg-devel] alsa input / output

Måns Rullgård mans
Sat Mar 24 22:11:34 CET 2007

Reimar D?ffinger <Reimar.Doeffinger at stud.uni-karlsruhe.de> writes:

> Hello,
> On Sat, Mar 24, 2007 at 02:17:58PM -0500, Rich Felker wrote:
>> as long as it's the lock-free thing, this sounds good! but is there
>> really such a thing as lock-free in this age where broken cpus like
>> ppc allow memory writes to take place in any order unless you insert
>> mem barriers? (and gcc is too broken to insert mem barriers itself
>> when you use the volatile keyword...)

Careful, the volatile keyword does not necessarily guarantee SMP-safe
code.  To be SMP-safe, you need both a compiler optimization barrier
and a CPU memory barrier.  The former makes sure the compiler doesn't
reorder instructions so a store happens later than you're expecting,
and the latter forces the CPU to finish executing all I/O instructions
and flush its write buffers.  The PPC has a very good instruction for
this called eieio: enforce in-order execution of I/O.

> Hm... is this really an issue? It can only be a problem with SMP or
> multicore systems, and even there I would hope the write reordering only
> concerns the main memory, not the caches and cache coherency...
> Someone have details on what kind of reordering these CPUs are actually
> doing?

Well, I have a 1000-page volume on parallel computer design in my

M?ns Rullg?rd
mans at mansr.com

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