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Macros
hevc_macros_msa.h File Reference

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Macros

#define HEVC_PCK_SW_SB2(in0, in1, out)
 
#define HEVC_PCK_SW_SB4(in0, in1, in2, in3, out)
 
#define HEVC_PCK_SW_SB8(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1)
 
#define HEVC_PCK_SW_SB12(in0, in1, in2, in3, in4, in5, in6, in7,in8, in9, in10, in11, out0, out1, out2)
 
#define HEVC_FILT_8TAP_SH(in0, in1, in2, in3,filt0, filt1, filt2, filt3)
 
#define HEVC_FILT_8TAP(in0, in1, in2, in3,filt0, filt1, filt2, filt3)
 
#define HEVC_FILT_4TAP(in0, in1, filt0, filt1)
 

Macro Definition Documentation

#define HEVC_PCK_SW_SB2 (   in0,
  in1,
  out 
)
#define HEVC_PCK_SW_SB4 (   in0,
  in1,
  in2,
  in3,
  out 
)
#define HEVC_PCK_SW_SB8 (   in0,
  in1,
  in2,
  in3,
  in4,
  in5,
  in6,
  in7,
  out0,
  out1 
)
Value:
{ \
v8i16 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
PCKEV_H4_SH(in0, in1, in2, in3, in4, in5, in6, in7, \
tmp0_m, tmp1_m, tmp2_m, tmp3_m); \
PCKEV_B2_SW(tmp1_m, tmp0_m, tmp3_m, tmp2_m, out0, out1); \
}
#define PCKEV_B2_SW(...)
#define PCKEV_H4_SH(...)

Definition at line 40 of file hevc_macros_msa.h.

Referenced by hevc_biwgt_copy_16multx4mult_msa(), hevc_biwgt_copy_4w_msa(), hevc_biwgt_copy_6w_msa(), hevc_biwgt_copy_8w_msa(), hevc_hv_biwgt_4t_4multx8mult_msa(), hevc_hv_biwgt_4t_6w_msa(), hevc_hv_biwgt_4t_8multx4mult_msa(), hevc_hv_biwgt_4t_8x6_msa(), hevc_hv_uniwgt_4t_6w_msa(), hevc_hv_uniwgt_4t_8multx4mult_msa(), hevc_hz_biwgt_4t_16w_msa(), hevc_hz_biwgt_4t_24w_msa(), hevc_hz_biwgt_4t_32w_msa(), hevc_hz_biwgt_4t_4x8multiple_msa(), hevc_hz_biwgt_4t_6w_msa(), hevc_hz_biwgt_4t_8x4multiple_msa(), hevc_hz_biwgt_8t_16w_msa(), hevc_hz_biwgt_8t_32w_msa(), hevc_hz_biwgt_8t_64w_msa(), hevc_hz_biwgt_8t_8w_msa(), hevc_hz_uniwgt_4t_16w_msa(), hevc_hz_uniwgt_4t_24w_msa(), hevc_hz_uniwgt_4t_32w_msa(), hevc_hz_uniwgt_4t_4x8multiple_msa(), hevc_hz_uniwgt_4t_6w_msa(), hevc_hz_uniwgt_4t_8x4multiple_msa(), hevc_vt_biwgt_4t_16w_msa(), hevc_vt_biwgt_4t_24w_msa(), hevc_vt_biwgt_4t_32w_msa(), hevc_vt_biwgt_4t_4x8multiple_msa(), hevc_vt_biwgt_4t_6w_msa(), hevc_vt_biwgt_4t_8x4multiple_msa(), hevc_vt_biwgt_8t_16multx2mult_msa(), hevc_vt_biwgt_8t_4w_msa(), hevc_vt_biwgt_8t_8w_msa(), hevc_vt_uniwgt_4t_16w_msa(), hevc_vt_uniwgt_4t_24w_msa(), hevc_vt_uniwgt_4t_32w_msa(), hevc_vt_uniwgt_4t_4x8multiple_msa(), hevc_vt_uniwgt_4t_6w_msa(), hevc_vt_uniwgt_4t_8x4multiple_msa(), hevc_vt_uniwgt_8t_16multx2mult_msa(), hevc_vt_uniwgt_8t_4w_msa(), and hevc_vt_uniwgt_8t_8w_msa().

#define HEVC_PCK_SW_SB12 (   in0,
  in1,
  in2,
  in3,
  in4,
  in5,
  in6,
  in7,
  in8,
  in9,
  in10,
  in11,
  out0,
  out1,
  out2 
)
Value:
{ \
v8i16 tmp0_m, tmp1_m, tmp2_m, tmp3_m, tmp4_m, tmp5_m; \
PCKEV_H4_SH(in0, in1, in2, in3, in4, in5, in6, in7, \
tmp0_m, tmp1_m, tmp2_m, tmp3_m); \
PCKEV_H2_SH(in8, in9, in10, in11, tmp4_m, tmp5_m); \
PCKEV_B2_SW(tmp1_m, tmp0_m, tmp3_m, tmp2_m, out0, out1); \
out2 = (v4i32) __msa_pckev_b((v16i8) tmp5_m, (v16i8) tmp4_m); \
}
#define PCKEV_H2_SH(...)
#define PCKEV_B2_SW(...)
#define PCKEV_H4_SH(...)

Definition at line 49 of file hevc_macros_msa.h.

Referenced by hevc_biwgt_copy_12w_msa(), hevc_biwgt_copy_8w_msa(), hevc_hv_uniwgt_4t_8x6_msa(), hevc_hz_biwgt_4t_12w_msa(), hevc_hz_biwgt_4t_8x6_msa(), hevc_hz_uniwgt_4t_12w_msa(), hevc_hz_uniwgt_4t_8x6_msa(), hevc_vt_biwgt_4t_12w_msa(), hevc_vt_biwgt_4t_8x6_msa(), hevc_vt_uniwgt_4t_12w_msa(), hevc_vt_uniwgt_4t_8x6_msa(), and hevc_vt_uniwgt_8t_12w_msa().

#define HEVC_FILT_8TAP_SH (   in0,
  in1,
  in2,
  in3,
  filt0,
  filt1,
  filt2,
  filt3 
)
Value:
( { \
v8i16 out_m; \
\
out_m = __msa_dotp_s_h((v16i8) in0, (v16i8) filt0); \
out_m = __msa_dpadd_s_h(out_m, (v16i8) in1, (v16i8) filt1); \
DPADD_SB2_SH(in2, in3, filt2, filt3, out_m, out_m); \
out_m; \
} )
#define DPADD_SB2_SH(...)

Definition at line 61 of file hevc_macros_msa.h.

Referenced by hevc_hz_uniwgt_8t_12w_msa(), hevc_hz_uniwgt_8t_16w_msa(), hevc_hz_uniwgt_8t_24w_msa(), hevc_hz_uniwgt_8t_32w_msa(), hevc_hz_uniwgt_8t_48w_msa(), hevc_hz_uniwgt_8t_4w_msa(), hevc_hz_uniwgt_8t_64w_msa(), and hevc_hz_uniwgt_8t_8w_msa().

#define HEVC_FILT_8TAP (   in0,
  in1,
  in2,
  in3,
  filt0,
  filt1,
  filt2,
  filt3 
)
Value:
( { \
v4i32 out_m; \
\
out_m = __msa_dotp_s_w((v8i16) in0, (v8i16) filt0); \
out_m = __msa_dpadd_s_w(out_m, (v8i16) in1, (v8i16) filt1); \
DPADD_SH2_SW(in2, in3, filt2, filt3, out_m, out_m); \
out_m; \
} )
#define DPADD_SH2_SW(...)

Definition at line 72 of file hevc_macros_msa.h.

Referenced by hevc_hv_8t_4w_msa(), hevc_hv_8t_8multx2mult_msa(), hevc_hv_bi_8t_4w_msa(), hevc_hv_bi_8t_8multx2mult_msa(), hevc_hv_biwgt_8t_4w_msa(), hevc_hv_biwgt_8t_8multx2mult_msa(), hevc_hv_uni_8t_4w_msa(), hevc_hv_uni_8t_8multx2mult_msa(), hevc_hv_uniwgt_8t_4w_msa(), and hevc_hv_uniwgt_8t_8multx2mult_msa().

#define HEVC_FILT_4TAP (   in0,
  in1,
  filt0,
  filt1 
)