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104 int main(
int argc,
char **argv)
109 const char *threads =
"auto";
120 if (cpu_flags_raw < 0)
124 int c =
getopt(argc, argv,
"c:t:");
146 if (cpu_flags_eff < 0)
void av_force_cpu_flags(int arg)
Disables cpu detection and forces the specified flags.
#define AV_CPU_FLAG_SSE3
Prescott SSE3 functions.
static atomic_int cpu_count
#define AV_CPU_FLAG_SSE3SLOW
SSE3 supported, but usually not faster.
#define AV_CPU_FLAG_3DNOW
AMD 3DNOW.
#define AV_CPU_FLAG_DOTPROD
int av_get_cpu_flags(void)
Return the flags which specify extensions supported by the CPU.
#define AV_CPU_FLAG_BMI1
Bit Manipulation Instruction Set 1.
static atomic_int cpu_flags
#define AV_CPU_FLAG_SSSE3
Conroe SSSE3 functions.
#define AV_CPU_FLAG_XOP
Bulldozer XOP functions.
int av_parse_cpu_caps(unsigned *flags, const char *s)
Parse CPU caps from a string and update the given AV_CPU_* flags based on that.
#define AV_CPU_FLAG_3DNOWEXT
AMD 3DNowExt.
it s the only field you need to keep assuming you have a context There is some magic you don t need to care about around this just let it vf type
#define AV_CPU_FLAG_SLOW_GATHER
CPU has slow gathers.
#define AV_CPU_FLAG_AVX512
AVX-512 functions: requires OS support even if YMM/ZMM registers aren't used.
static int getopt(int argc, char *argv[], char *opts)
#define AV_CPU_FLAG_ARMV6
#define AV_CPU_FLAG_SSE4
Penryn SSE4.1 functions.
static void print_cpu_flags(int cpu_flags, const char *type)
#define AV_CPU_FLAG_AVX512ICL
F/CD/BW/DQ/VL/VNNI/IFMA/VBMI/VBMI2/VPOPCNTDQ/BITALG/GFNI/VAES/VPCLMULQDQ.
#define AV_CPU_FLAG_CMOV
supports cmov instruction
#define AV_CPU_FLAG_ALTIVEC
standard
Undefined Behavior In the C some operations are like signed integer dereferencing freed accessing outside allocated Undefined Behavior must not occur in a C it is not safe even if the output of undefined operations is unused The unsafety may seem nit picking but Optimizing compilers have in fact optimized code on the assumption that no undefined Behavior occurs Optimizing code based on wrong assumptions can and has in some cases lead to effects beyond the output of computations The signed integer overflow problem in speed critical code Code which is highly optimized and works with signed integers sometimes has the problem that often the output of the computation does not c
#define AV_CPU_FLAG_SSE2
PIV SSE2 functions.
#define AV_CPU_FLAG_SETEND
int main(int argc, char **argv)
#define AV_CPU_FLAG_AVXSLOW
AVX supported, but slow when using YMM registers (e.g. Bulldozer)
#define AV_CPU_FLAG_AVX
AVX functions: requires OS support even if YMM registers aren't used.
#define AV_CPU_FLAG_FMA4
Bulldozer FMA4 functions.
#define AV_CPU_FLAG_AVX2
AVX2 functions: requires OS support even if YMM registers aren't used.
#define AV_CPU_FLAG_SSE2SLOW
SSE2 supported, but usually not faster.
printf("static const uint8_t my_array[100] = {\n")
#define AV_CPU_FLAG_FMA3
Haswell FMA3 functions.
#define i(width, name, range_min, range_max)
#define AV_CPU_FLAG_SSE42
Nehalem SSE4.2 functions.
#define AV_CPU_FLAG_ARMV8
#define AV_CPU_FLAG_ATOM
Atom processor, some SSSE3 instructions are slower.
#define AV_CPU_FLAG_VFPV3
#define AV_CPU_FLAG_ARMV5TE
#define AV_CPU_FLAG_MMX
standard MMX
static const struct @354 cpu_flag_tab[]
#define AV_CPU_FLAG_AESNI
Advanced Encryption Standard functions.
#define AV_CPU_FLAG_SSE
SSE functions.
#define AV_CPU_FLAG_MMXEXT
SSE integer functions or AMD MMX ext.
#define AV_CPU_FLAG_BMI2
Bit Manipulation Instruction Set 2.
#define AV_CPU_FLAG_VFP_VM
VFPv2 vector mode, deprecated in ARMv7-A and unavailable in various CPUs implementations.
#define flags(name, subs,...)
#define AV_CPU_FLAG_ARMV6T2