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blockdsp.c
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1 /*
2  * Copyright (c) 2002 Brian Foley
3  * Copyright (c) 2002 Dieter Shirley
4  * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org>
5  *
6  * This file is part of FFmpeg.
7  *
8  * FFmpeg is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU Lesser General Public
10  * License as published by the Free Software Foundation; either
11  * version 2.1 of the License, or (at your option) any later version.
12  *
13  * FFmpeg is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16  * Lesser General Public License for more details.
17  *
18  * You should have received a copy of the GNU Lesser General Public
19  * License along with FFmpeg; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21  */
22 
23 #include "config.h"
24 
25 #include <string.h>
26 
27 #include "libavutil/attributes.h"
28 #include "libavutil/cpu.h"
29 #include "libavutil/mem.h"
30 #include "libavutil/ppc/cpu.h"
32 
33 #include "libavcodec/blockdsp.h"
34 
35 /* ***** WARNING ***** WARNING ***** WARNING ***** */
36 /*
37  * clear_blocks_dcbz32_ppc will not work properly on PowerPC processors with
38  * a cache line size not equal to 32 bytes. Fortunately all processors used
39  * by Apple up to at least the 7450 (AKA second generation G4) use 32-byte
40  * cache lines. This is due to the use of the 'dcbz' instruction. It simply
41  * clears a single cache line to zero, so you need to know the cache line
42  * size to use it! It's absurd, but it's fast...
43  *
44  * update 24/06/2003: Apple released the G5 yesterday, with a PPC970.
45  * cache line size: 128 bytes. Oups.
46  * The semantics of dcbz was changed, it always clears 32 bytes. So the function
47  * below will work, but will be slow. So I fixed check_dcbz_effect to use dcbzl,
48  * which is defined to clear a cache line (as dcbz before). So we can still
49  * distinguish, and use dcbz (32 bytes) or dcbzl (one cache line) as required.
50  *
51  * see <http://developer.apple.com/technotes/tn/tn2087.html>
52  * and <http://developer.apple.com/technotes/tn/tn2086.html>
53  */
54 static void clear_blocks_dcbz32_ppc(int16_t *blocks)
55 {
56  register int misal = (unsigned long) blocks & 0x00000010, i = 0;
57 
58  if (misal) {
59  ((unsigned long *) blocks)[0] = 0L;
60  ((unsigned long *) blocks)[1] = 0L;
61  ((unsigned long *) blocks)[2] = 0L;
62  ((unsigned long *) blocks)[3] = 0L;
63  i += 16;
64  }
65  for (; i < sizeof(int16_t) * 6 * 64 - 31; i += 32)
66  __asm__ volatile ("dcbz %0,%1" :: "b" (blocks), "r" (i) : "memory");
67  if (misal) {
68  ((unsigned long *) blocks)[188] = 0L;
69  ((unsigned long *) blocks)[189] = 0L;
70  ((unsigned long *) blocks)[190] = 0L;
71  ((unsigned long *) blocks)[191] = 0L;
72  i += 16;
73  }
74 }
75 
76 /* Same as above, when dcbzl clears a whole 128 bytes cache line
77  * i.e. the PPC970 AKA G5. */
78 static void clear_blocks_dcbz128_ppc(int16_t *blocks)
79 {
80 #if HAVE_DCBZL
81  register int misal = (unsigned long) blocks & 0x0000007f, i = 0;
82 
83  if (misal) {
84  /* We could probably also optimize this case,
85  * but there's not much point as the machines
86  * aren't available yet (2003-06-26). */
87  memset(blocks, 0, sizeof(int16_t) * 6 * 64);
88  } else {
89  for (; i < sizeof(int16_t) * 6 * 64; i += 128)
90  __asm__ volatile ("dcbzl %0,%1" :: "b" (blocks), "r" (i) : "memory");
91  }
92 #else
93  memset(blocks, 0, sizeof(int16_t) * 6 * 64);
94 #endif
95 }
96 
97 /* Check dcbz report how many bytes are set to 0 by dcbz. */
98 /* update 24/06/2003: Replace dcbz by dcbzl to get the intended effect
99  * (Apple "fixed" dcbz). Unfortunately this cannot be used unless the
100  * assembler knows about dcbzl ... */
101 static long check_dcbzl_effect(void)
102 {
103  long count = 0;
104 #if HAVE_DCBZL
105  register char *fakedata = av_malloc(1024);
106  register char *fakedata_middle;
107  register long zero = 0, i = 0;
108 
109  if (!fakedata)
110  return 0L;
111 
112  fakedata_middle = fakedata + 512;
113 
114  memset(fakedata, 0xFF, 1024);
115 
116  /* Below the constraint "b" seems to mean "address base register"
117  * in gcc-3.3 / RS/6000 speaks. Seems to avoid using r0, so.... */
118  __asm__ volatile ("dcbzl %0, %1" :: "b" (fakedata_middle), "r" (zero));
119 
120  for (i = 0; i < 1024; i++)
121  if (fakedata[i] == (char) 0)
122  count++;
123 
124  av_free(fakedata);
125 #endif
126 
127  return count;
128 }
129 
130 #if HAVE_ALTIVEC
131 static void clear_block_altivec(int16_t *block)
132 {
133  LOAD_ZERO;
134  vec_st(zero_s16v, 0, block);
135  vec_st(zero_s16v, 16, block);
136  vec_st(zero_s16v, 32, block);
137  vec_st(zero_s16v, 48, block);
138  vec_st(zero_s16v, 64, block);
139  vec_st(zero_s16v, 80, block);
140  vec_st(zero_s16v, 96, block);
141  vec_st(zero_s16v, 112, block);
142 }
143 #endif /* HAVE_ALTIVEC */
144 
146 {
147  // common optimizations whether AltiVec is available or not
148  switch (check_dcbzl_effect()) {
149  case 32:
151  break;
152  case 128:
154  break;
155  default:
156  break;
157  }
158 
159 #if HAVE_ALTIVEC
161  return;
162 
163  c->clear_block = clear_block_altivec;
164 #endif /* HAVE_ALTIVEC */
165 }
void(* clear_block)(int16_t *block)
Definition: blockdsp.h:36
Memory handling functions.
static long check_dcbzl_effect(void)
Definition: blockdsp.c:101
void(* clear_blocks)(int16_t *blocks)
Definition: blockdsp.h:37
#define LOAD_ZERO
Definition: util_altivec.h:45
Macro definitions for various function/variable attributes.
static int16_t block[64]
Definition: dct.c:115
#define av_cold
Definition: attributes.h:82
#define av_malloc(s)
#define PPC_ALTIVEC(flags)
Definition: cpu.h:26
#define zero
Definition: regdef.h:64
GLsizei count
Definition: opengl_enc.c:109
static void clear_blocks_dcbz128_ppc(int16_t *blocks)
Definition: blockdsp.c:78
#define L(x)
Definition: vp56_arith.h:36
static void clear_blocks_dcbz32_ppc(int16_t *blocks)
Definition: blockdsp.c:54
int av_get_cpu_flags(void)
Return the flags which specify extensions supported by the CPU.
Definition: cpu.c:92
Contains misc utility macros and inline functions.
#define zero_s16v
Definition: util_altivec.h:50
static double c[64]
av_cold void ff_blockdsp_init_ppc(BlockDSPContext *c)
Definition: blockdsp.c:145
#define av_free(p)