138 const char *threads =
"auto";
149 if (cpu_flags_raw < 0)
153 int c =
getopt(argc, argv,
"c:t:");
175 if (cpu_flags_eff < 0)
181#if ARCH_AARCH64 && HAVE_SVE
183 printf(
"sve_vector_length = %d\n", 8 * ff_aarch64_sve_length());
185#if ARCH_AARCH64 && HAVE_SME
187 printf(
"sme_vector_length = %d\n", 8 * ff_aarch64_sme_length());
189#if ARCH_RISCV && HAVE_RVV
191 size_t bytes = ff_get_rv_vlenb();
193 printf(
"rv_vlenb = %zu (%zu bits)\n", bytes, 8 * bytes);
#define flags(name, subs,...)
#define i(width, name, range_min, range_max)
__device__ int printf(const char *,...)
static int getopt(int argc, char *argv[], const char *opts)
void av_force_cpu_flags(int arg)
Disables cpu detection and forces the specified flags.
static atomic_int cpu_flags
int av_parse_cpu_caps(unsigned *flags, const char *s)
Parse CPU caps from a string and update the given AV_CPU_* flags based on that.
static atomic_int cpu_count
int av_get_cpu_flags(void)
Return the flags which specify extensions supported by the CPU.
#define AV_CPU_FLAG_DOTPROD
#define AV_CPU_FLAG_RVV_I64
Vectors of 64-bit int's */.
#define AV_CPU_FLAG_ARMV5TE
#define AV_CPU_FLAG_FMA3
Haswell FMA3 functions.
#define AV_CPU_FLAG_SSE2
PIV SSE2 functions.
#define AV_CPU_FLAG_BMI1
Bit Manipulation Instruction Set 1.
#define AV_CPU_FLAG_RVI
I (full GPR bank)
#define AV_CPU_FLAG_VFPV3
#define AV_CPU_FLAG_SSE3SLOW
SSE3 supported, but usually not faster than regular MMX/SSE (e.g.
#define AV_CPU_FLAG_AVX512
AVX-512 functions: requires OS support even if YMM/ZMM registers aren't used.
#define AV_CPU_FLAG_SSE42
Nehalem SSE4.2 functions.
#define AV_CPU_FLAG_CMOV
supports cmov instruction
#define AV_CPU_FLAG_SSE
SSE functions.
#define AV_CPU_FLAG_RVB
B (bit manipulations)
#define AV_CPU_FLAG_RVB_BASIC
Basic bit-manipulations.
#define AV_CPU_FLAG_SSE4
Penryn SSE4.1 functions.
#define AV_CPU_FLAG_FMA4
Bulldozer FMA4 functions.
#define AV_CPU_FLAG_RVV_I32
Vectors of 8/16/32-bit int's */.
#define AV_CPU_FLAG_VSX
ISA 2.06.
#define AV_CPU_FLAG_POWER8
ISA 2.07.
#define AV_CPU_FLAG_SETEND
#define AV_CPU_FLAG_BMI2
Bit Manipulation Instruction Set 2.
#define AV_CPU_FLAG_SSE2SLOW
SSE2 supported, but usually not faster than regular MMX/SSE (e.g.
#define AV_CPU_FLAG_MMXEXT
SSE integer functions or AMD MMX ext.
#define AV_CPU_FLAG_SSE3
Prescott SSE3 functions.
#define AV_CPU_FLAG_AESNI
Advanced Encryption Standard functions.
#define AV_CPU_FLAG_SME_I16I64
#define AV_CPU_FLAG_ARMV6T2
#define AV_CPU_FLAG_3DNOWEXT
AMD 3DNowExt.
#define AV_CPU_FLAG_XOP
Bulldozer XOP functions.
#define AV_CPU_FLAG_ALTIVEC
standard
#define AV_CPU_FLAG_ATOM
Atom processor, some SSSE3 instructions are slower.
#define AV_CPU_FLAG_VFP_VM
VFPv2 vector mode, deprecated in ARMv7-A and unavailable in various CPUs implementations.
#define AV_CPU_FLAG_AVX2
AVX2 functions: requires OS support even if YMM registers aren't used.
#define AV_CPU_FLAG_SSSE3
Conroe SSSE3 functions.
#define AV_CPU_FLAG_ARM_CRC
#define AV_CPU_FLAG_AVX512ICL
F/CD/BW/DQ/VL/VNNI/IFMA/VBMI/VBMI2/VPOPCNTDQ/BITALG/GFNI/VAES/VPCLMULQDQ.
#define AV_CPU_FLAG_CLMUL
Carry-less Multiplication instruction.
#define AV_CPU_FLAG_ARMV8
#define AV_CPU_FLAG_PMULL
#define AV_CPU_FLAG_SLOW_GATHER
CPU has slow gathers.
#define AV_CPU_FLAG_SIMD128
#define AV_CPU_FLAG_RV_ZVBB
Vector basic bit-manipulations.
#define AV_CPU_FLAG_AVXSLOW
AVX supported, but slow when using YMM registers (e.g. Bulldozer)
#define AV_CPU_FLAG_RVV_F32
Vectors of float's */.
#define AV_CPU_FLAG_ARMV6
#define AV_CPU_FLAG_MMX
standard MMX
#define AV_CPU_FLAG_RVV_F64
Vectors of double's.
#define AV_CPU_FLAG_3DNOW
AMD 3DNOW.
#define AV_CPU_FLAG_AVX
AVX functions: requires OS support even if YMM registers aren't used.
#define AV_CPU_FLAG_RV_MISALIGNED
Fast misaligned accesses.
static const struct @274126366234264103360351317125224231232203050147 cpu_flag_tab[]
static void print_cpu_flags(int cpu_flags, const char *type)