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cpu.c
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1/*
2 * This file is part of FFmpeg.
3 *
4 * FFmpeg is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2.1 of the License, or (at your option) any later version.
8 *
9 * FFmpeg is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with FFmpeg; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#include <stdio.h>
20
21#include "config.h"
22
23#include "libavutil/cpu.h"
24#include "libavutil/avstring.h"
25
26#if ARCH_AARCH64
28#elif ARCH_RISCV
29#include "libavutil/riscv/cpu.h"
30#endif
31
32#if HAVE_UNISTD_H
33#include <unistd.h>
34#endif
35#if !HAVE_GETOPT
36#include "compat/getopt.c"
37#endif
38
39static const struct {
40 int flag;
41 const char *name;
42} cpu_flag_tab[] = {
43#if ARCH_AARCH64
44 { AV_CPU_FLAG_ARMV8, "armv8" },
45 { AV_CPU_FLAG_NEON, "neon" },
46 { AV_CPU_FLAG_VFP, "vfp" },
47 { AV_CPU_FLAG_DOTPROD, "dotprod" },
48 { AV_CPU_FLAG_I8MM, "i8mm" },
49 { AV_CPU_FLAG_SVE, "sve" },
50 { AV_CPU_FLAG_SVE2, "sve2" },
51 { AV_CPU_FLAG_SME, "sme" },
52 { AV_CPU_FLAG_SME_I16I64, "sme_i16i64" },
53 { AV_CPU_FLAG_ARM_CRC, "crc" },
54 { AV_CPU_FLAG_SME2, "sme2" },
55 { AV_CPU_FLAG_PMULL, "pmull" },
56 { AV_CPU_FLAG_EOR3, "eor3" },
57#elif ARCH_ARM
58 { AV_CPU_FLAG_ARMV5TE, "armv5te" },
59 { AV_CPU_FLAG_ARMV6, "armv6" },
60 { AV_CPU_FLAG_ARMV6T2, "armv6t2" },
61 { AV_CPU_FLAG_VFP, "vfp" },
62 { AV_CPU_FLAG_VFP_VM, "vfp_vm" },
63 { AV_CPU_FLAG_VFPV3, "vfpv3" },
64 { AV_CPU_FLAG_NEON, "neon" },
65 { AV_CPU_FLAG_SETEND, "setend" },
66#elif ARCH_PPC
67 { AV_CPU_FLAG_ALTIVEC, "altivec" },
68 { AV_CPU_FLAG_VSX, "vsx" },
69 { AV_CPU_FLAG_POWER8, "power8" },
70#elif ARCH_MIPS
71 { AV_CPU_FLAG_MMI, "mmi" },
72 { AV_CPU_FLAG_MSA, "msa" },
73#elif ARCH_X86
74 { AV_CPU_FLAG_MMX, "mmx" },
75 { AV_CPU_FLAG_MMXEXT, "mmxext" },
76 { AV_CPU_FLAG_SSE, "sse" },
77 { AV_CPU_FLAG_SSE2, "sse2" },
78 { AV_CPU_FLAG_SSE2SLOW, "sse2slow" },
79 { AV_CPU_FLAG_SSE3, "sse3" },
80 { AV_CPU_FLAG_SSE3SLOW, "sse3slow" },
81 { AV_CPU_FLAG_SSSE3, "ssse3" },
82 { AV_CPU_FLAG_ATOM, "atom" },
83 { AV_CPU_FLAG_SSE4, "sse4.1" },
84 { AV_CPU_FLAG_SSE42, "sse4.2" },
85 { AV_CPU_FLAG_AVX, "avx" },
86 { AV_CPU_FLAG_AVXSLOW, "avxslow" },
87 { AV_CPU_FLAG_XOP, "xop" },
88 { AV_CPU_FLAG_FMA3, "fma3" },
89 { AV_CPU_FLAG_FMA4, "fma4" },
90 { AV_CPU_FLAG_3DNOW, "3dnow" },
91 { AV_CPU_FLAG_3DNOWEXT, "3dnowext" },
92 { AV_CPU_FLAG_CMOV, "cmov" },
93 { AV_CPU_FLAG_AVX2, "avx2" },
94 { AV_CPU_FLAG_BMI1, "bmi1" },
95 { AV_CPU_FLAG_BMI2, "bmi2" },
96 { AV_CPU_FLAG_AESNI, "aesni" },
97 { AV_CPU_FLAG_CLMUL, "clmul" },
98 { AV_CPU_FLAG_AVX512, "avx512" },
99 { AV_CPU_FLAG_AVX512ICL, "avx512icl" },
100 { AV_CPU_FLAG_SLOW_GATHER, "slowgather" },
101#elif ARCH_LOONGARCH
102 { AV_CPU_FLAG_LSX, "lsx" },
103 { AV_CPU_FLAG_LASX, "lasx" },
104#elif ARCH_RISCV
105 { AV_CPU_FLAG_RVI, "rvi" },
106 { AV_CPU_FLAG_RVB_BASIC, "zbb" },
107 { AV_CPU_FLAG_RVB, "rvb" },
108 { AV_CPU_FLAG_RVV_I32, "zve32x" },
109 { AV_CPU_FLAG_RVV_F32, "zve32f" },
110 { AV_CPU_FLAG_RVV_I64, "zve64x" },
111 { AV_CPU_FLAG_RVV_F64, "zve64d" },
112 { AV_CPU_FLAG_RV_ZVBB, "zvbb" },
113 { AV_CPU_FLAG_RV_MISALIGNED, "misaligned" },
114#elif ARCH_WASM
115 { AV_CPU_FLAG_SIMD128, "simd128" },
116#endif
117 { 0 }
119
120static void print_cpu_flags(int cpu_flags, const char *type)
121{
122 int i;
123
124 printf("cpu_flags(%s) = 0x%08X\n", type, cpu_flags);
125 printf("cpu_flags_str(%s) =", type);
126 for (i = 0; cpu_flag_tab[i].flag; i++)
128 printf(" %s", cpu_flag_tab[i].name);
129 printf("\n");
130}
131
132
133int main(int argc, char **argv)
134{
135 int cpu_flags_raw = av_get_cpu_flags();
136 int cpu_flags_eff;
137 int cpu_count = av_cpu_count();
138 const char *threads = "auto";
139 int i;
140
141 for(i = 0; cpu_flag_tab[i].flag; i++) {
142 unsigned tmp = 0;
144 fprintf(stderr, "Table missing %s\n", cpu_flag_tab[i].name);
145 return 4;
146 }
147 }
148
149 if (cpu_flags_raw < 0)
150 return 1;
151
152 for (;;) {
153 int c = getopt(argc, argv, "c:t:");
154 if (c == -1)
155 break;
156 switch (c) {
157 case 'c':
158 {
159 unsigned flags = av_get_cpu_flags();
160 if (av_parse_cpu_caps(&flags, optarg) < 0)
161 return 2;
162
164 break;
165 }
166 case 't':
167 {
168 threads = optarg;
169 }
170 }
171 }
172
173 cpu_flags_eff = av_get_cpu_flags();
174
175 if (cpu_flags_eff < 0)
176 return 3;
177
178 print_cpu_flags(cpu_flags_raw, "raw");
179 print_cpu_flags(cpu_flags_eff, "effective");
180 printf("threads = %s (cpu_count = %d)\n", threads, cpu_count);
181#if ARCH_AARCH64 && HAVE_SVE
182 if (cpu_flags_raw & AV_CPU_FLAG_SVE)
183 printf("sve_vector_length = %d\n", 8 * ff_aarch64_sve_length());
184#endif
185#if ARCH_AARCH64 && HAVE_SME
186 if (cpu_flags_raw & AV_CPU_FLAG_SME)
187 printf("sme_vector_length = %d\n", 8 * ff_aarch64_sme_length());
188#endif
189#if ARCH_RISCV && HAVE_RVV
190 if (cpu_flags_raw & AV_CPU_FLAG_RVV_I32) {
191 size_t bytes = ff_get_rv_vlenb();
192
193 printf("rv_vlenb = %zu (%zu bits)\n", bytes, 8 * bytes);
194 }
195#endif
196
197 return 0;
198}
#define flag(name)
Definition cbs_h264.c:60
#define flags(name, subs,...)
Definition cbs_h264.c:74
#define i(width, name, range_min, range_max)
Definition cbs_h264.c:63
__device__ int printf(const char *,...)
int main
Definition dovi_rpuenc.c:38
static int getopt(int argc, char *argv[], const char *opts)
Definition getopt.c:41
static char * optarg
Definition getopt.c:39
cl_device_type type
void av_force_cpu_flags(int arg)
Disables cpu detection and forces the specified flags.
Definition cpu.c:81
static atomic_int cpu_flags
Definition cpu.c:56
int av_parse_cpu_caps(unsigned *flags, const char *s)
Parse CPU caps from a string and update the given AV_CPU_* flags based on that.
Definition cpu.c:119
static atomic_int cpu_count
Definition cpu.c:57
int av_get_cpu_flags(void)
Return the flags which specify extensions supported by the CPU.
Definition cpu.c:109
int av_cpu_count(void)
Definition cpu.c:228
#define AV_CPU_FLAG_DOTPROD
Definition cpu.h:76
#define AV_CPU_FLAG_RVV_I64
Vectors of 64-bit int's *‍/.
Definition cpu.h:99
#define AV_CPU_FLAG_ARMV5TE
Definition cpu.h:68
#define AV_CPU_FLAG_FMA3
Haswell FMA3 functions.
Definition cpu.h:57
#define AV_CPU_FLAG_SSE2
PIV SSE2 functions.
Definition cpu.h:37
#define AV_CPU_FLAG_BMI1
Bit Manipulation Instruction Set 1.
Definition cpu.h:58
#define AV_CPU_FLAG_SVE
Definition cpu.h:78
#define AV_CPU_FLAG_RVI
I (full GPR bank)
Definition cpu.h:96
#define AV_CPU_FLAG_VFPV3
Definition cpu.h:72
#define AV_CPU_FLAG_LASX
Definition cpu.h:93
#define AV_CPU_FLAG_SSE3SLOW
SSE3 supported, but usually not faster than regular MMX/SSE (e.g.
Definition cpu.h:42
#define AV_CPU_FLAG_AVX512
AVX-512 functions: requires OS support even if YMM/ZMM registers aren't used.
Definition cpu.h:60
#define AV_CPU_FLAG_VFP
Definition cpu.h:71
#define AV_CPU_FLAG_SSE42
Nehalem SSE4.2 functions.
Definition cpu.h:48
#define AV_CPU_FLAG_NEON
Definition cpu.h:73
#define AV_CPU_FLAG_I8MM
Definition cpu.h:77
#define AV_CPU_FLAG_CMOV
supports cmov instruction
Definition cpu.h:55
#define AV_CPU_FLAG_SVE2
Definition cpu.h:79
#define AV_CPU_FLAG_SSE
SSE functions.
Definition cpu.h:36
#define AV_CPU_FLAG_RVB
B (bit manipulations)
Definition cpu.h:104
#define AV_CPU_FLAG_RVB_BASIC
Basic bit-manipulations.
Definition cpu.h:101
#define AV_CPU_FLAG_SSE4
Penryn SSE4.1 functions.
Definition cpu.h:47
#define AV_CPU_FLAG_FMA4
Bulldozer FMA4 functions.
Definition cpu.h:54
#define AV_CPU_FLAG_RVV_I32
Vectors of 8/16/32-bit int's *‍/.
Definition cpu.h:97
#define AV_CPU_FLAG_VSX
ISA 2.06.
Definition cpu.h:65
#define AV_CPU_FLAG_POWER8
ISA 2.07.
Definition cpu.h:66
#define AV_CPU_FLAG_SETEND
Definition cpu.h:84
#define AV_CPU_FLAG_BMI2
Bit Manipulation Instruction Set 2.
Definition cpu.h:59
#define AV_CPU_FLAG_SSE2SLOW
SSE2 supported, but usually not faster than regular MMX/SSE (e.g.
Definition cpu.h:38
#define AV_CPU_FLAG_MMXEXT
SSE integer functions or AMD MMX ext.
Definition cpu.h:33
#define AV_CPU_FLAG_SSE3
Prescott SSE3 functions.
Definition cpu.h:41
#define AV_CPU_FLAG_AESNI
Advanced Encryption Standard functions.
Definition cpu.h:49
#define AV_CPU_FLAG_LSX
Definition cpu.h:92
#define AV_CPU_FLAG_SME_I16I64
Definition cpu.h:83
#define AV_CPU_FLAG_ARMV6T2
Definition cpu.h:70
#define AV_CPU_FLAG_3DNOWEXT
AMD 3DNowExt.
Definition cpu.h:40
#define AV_CPU_FLAG_XOP
Bulldozer XOP functions.
Definition cpu.h:53
#define AV_CPU_FLAG_ALTIVEC
standard
Definition cpu.h:64
#define AV_CPU_FLAG_EOR3
Definition cpu.h:86
#define AV_CPU_FLAG_ATOM
Atom processor, some SSSE3 instructions are slower.
Definition cpu.h:46
#define AV_CPU_FLAG_VFP_VM
VFPv2 vector mode, deprecated in ARMv7-A and unavailable in various CPUs implementations.
Definition cpu.h:75
#define AV_CPU_FLAG_AVX2
AVX2 functions: requires OS support even if YMM registers aren't used.
Definition cpu.h:56
#define AV_CPU_FLAG_SME2
Definition cpu.h:82
#define AV_CPU_FLAG_SSSE3
Conroe SSSE3 functions.
Definition cpu.h:44
#define AV_CPU_FLAG_ARM_CRC
Definition cpu.h:81
#define AV_CPU_FLAG_AVX512ICL
F/CD/BW/DQ/VL/VNNI/IFMA/VBMI/VBMI2/VPOPCNTDQ/BITALG/GFNI/VAES/VPCLMULQDQ.
Definition cpu.h:61
#define AV_CPU_FLAG_CLMUL
Carry-less Multiplication instruction.
Definition cpu.h:50
#define AV_CPU_FLAG_ARMV8
Definition cpu.h:74
#define AV_CPU_FLAG_PMULL
Definition cpu.h:85
#define AV_CPU_FLAG_SLOW_GATHER
CPU has slow gathers.
Definition cpu.h:62
#define AV_CPU_FLAG_SIMD128
Definition cpu.h:107
#define AV_CPU_FLAG_MSA
Definition cpu.h:89
#define AV_CPU_FLAG_RV_ZVBB
Vector basic bit-manipulations.
Definition cpu.h:102
#define AV_CPU_FLAG_AVXSLOW
AVX supported, but slow when using YMM registers (e.g. Bulldozer)
Definition cpu.h:52
#define AV_CPU_FLAG_RVV_F32
Vectors of float's *‍/.
Definition cpu.h:98
#define AV_CPU_FLAG_ARMV6
Definition cpu.h:69
#define AV_CPU_FLAG_SME
Definition cpu.h:80
#define AV_CPU_FLAG_MMX
standard MMX
Definition cpu.h:32
#define AV_CPU_FLAG_MMI
Definition cpu.h:88
#define AV_CPU_FLAG_RVV_F64
Vectors of double's.
Definition cpu.h:100
#define AV_CPU_FLAG_3DNOW
AMD 3DNOW.
Definition cpu.h:35
#define AV_CPU_FLAG_AVX
AVX functions: requires OS support even if YMM registers aren't used.
Definition cpu.h:51
#define AV_CPU_FLAG_RV_MISALIGNED
Fast misaligned accesses.
Definition cpu.h:103
static const struct @274126366234264103360351317125224231232203050147 cpu_flag_tab[]
static void print_cpu_flags(int cpu_flags, const char *type)
Definition cpu.c:120
const char * name
Definition qsvenc.c:142
static uint8_t tmp[40]
Definition aes_ctr.c:52
static double c[64]