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vp9_idct_msa.c
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1 /*
2  * Copyright (c) 2015 Shivraj Patil (Shivraj.Patil@imgtec.com)
3  *
4  * This file is part of FFmpeg.
5  *
6  * FFmpeg is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * FFmpeg is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with FFmpeg; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19  */
20 
21 #include <string.h>
22 #include "libavcodec/vp9dsp.h"
23 #include "libavutil/mips/generic_macros_msa.h"
24 #include "vp9dsp_mips.h"
25 
26 #define VP9_DCT_CONST_BITS 14
27 #define ROUND_POWER_OF_TWO(value, n) (((value) + (1 << ((n) - 1))) >> (n))
28 
29 static const int32_t cospi_1_64 = 16364;
30 static const int32_t cospi_2_64 = 16305;
31 static const int32_t cospi_3_64 = 16207;
32 static const int32_t cospi_4_64 = 16069;
33 static const int32_t cospi_5_64 = 15893;
34 static const int32_t cospi_6_64 = 15679;
35 static const int32_t cospi_7_64 = 15426;
36 static const int32_t cospi_8_64 = 15137;
37 static const int32_t cospi_9_64 = 14811;
38 static const int32_t cospi_10_64 = 14449;
39 static const int32_t cospi_11_64 = 14053;
40 static const int32_t cospi_12_64 = 13623;
41 static const int32_t cospi_13_64 = 13160;
42 static const int32_t cospi_14_64 = 12665;
43 static const int32_t cospi_15_64 = 12140;
44 static const int32_t cospi_16_64 = 11585;
45 static const int32_t cospi_17_64 = 11003;
46 static const int32_t cospi_18_64 = 10394;
47 static const int32_t cospi_19_64 = 9760;
48 static const int32_t cospi_20_64 = 9102;
49 static const int32_t cospi_21_64 = 8423;
50 static const int32_t cospi_22_64 = 7723;
51 static const int32_t cospi_23_64 = 7005;
52 static const int32_t cospi_24_64 = 6270;
53 static const int32_t cospi_25_64 = 5520;
54 static const int32_t cospi_26_64 = 4756;
55 static const int32_t cospi_27_64 = 3981;
56 static const int32_t cospi_28_64 = 3196;
57 static const int32_t cospi_29_64 = 2404;
58 static const int32_t cospi_30_64 = 1606;
59 static const int32_t cospi_31_64 = 804;
60 
61 // 16384 * sqrt(2) * sin(kPi/9) * 2 / 3
62 static const int32_t sinpi_1_9 = 5283;
63 static const int32_t sinpi_2_9 = 9929;
64 static const int32_t sinpi_3_9 = 13377;
65 static const int32_t sinpi_4_9 = 15212;
66 
67 #define VP9_DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \
68 { \
69  v8i16 k0_m = __msa_fill_h(cnst0); \
70  v4i32 s0_m, s1_m, s2_m, s3_m; \
71  \
72  s0_m = (v4i32) __msa_fill_h(cnst1); \
73  k0_m = __msa_ilvev_h((v8i16) s0_m, k0_m); \
74  \
75  ILVRL_H2_SW((-reg1), reg0, s1_m, s0_m); \
76  ILVRL_H2_SW(reg0, reg1, s3_m, s2_m); \
77  DOTP_SH2_SW(s1_m, s0_m, k0_m, k0_m, s1_m, s0_m); \
78  SRARI_W2_SW(s1_m, s0_m, VP9_DCT_CONST_BITS); \
79  out0 = __msa_pckev_h((v8i16) s0_m, (v8i16) s1_m); \
80  \
81  DOTP_SH2_SW(s3_m, s2_m, k0_m, k0_m, s1_m, s0_m); \
82  SRARI_W2_SW(s1_m, s0_m, VP9_DCT_CONST_BITS); \
83  out1 = __msa_pckev_h((v8i16) s0_m, (v8i16) s1_m); \
84 }
85 
86 #define VP9_DOT_ADD_SUB_SRARI_PCK(in0, in1, in2, in3, in4, in5, in6, in7, \
87  dst0, dst1, dst2, dst3) \
88 { \
89  v4i32 tp0_m, tp1_m, tp2_m, tp3_m, tp4_m; \
90  v4i32 tp5_m, tp6_m, tp7_m, tp8_m, tp9_m; \
91  \
92  DOTP_SH4_SW(in0, in1, in0, in1, in4, in4, in5, in5, \
93  tp0_m, tp2_m, tp3_m, tp4_m); \
94  DOTP_SH4_SW(in2, in3, in2, in3, in6, in6, in7, in7, \
95  tp5_m, tp6_m, tp7_m, tp8_m); \
96  BUTTERFLY_4(tp0_m, tp3_m, tp7_m, tp5_m, tp1_m, tp9_m, tp7_m, tp5_m); \
97  BUTTERFLY_4(tp2_m, tp4_m, tp8_m, tp6_m, tp3_m, tp0_m, tp4_m, tp2_m); \
98  SRARI_W4_SW(tp1_m, tp9_m, tp7_m, tp5_m, VP9_DCT_CONST_BITS); \
99  SRARI_W4_SW(tp3_m, tp0_m, tp4_m, tp2_m, VP9_DCT_CONST_BITS); \
100  PCKEV_H4_SH(tp1_m, tp3_m, tp9_m, tp0_m, tp7_m, tp4_m, tp5_m, tp2_m, \
101  dst0, dst1, dst2, dst3); \
102 }
103 
104 #define VP9_DOT_SHIFT_RIGHT_PCK_H(in0, in1, in2) \
105 ( { \
106  v8i16 dst_m; \
107  v4i32 tp0_m, tp1_m; \
108  \
109  DOTP_SH2_SW(in0, in1, in2, in2, tp1_m, tp0_m); \
110  SRARI_W2_SW(tp1_m, tp0_m, VP9_DCT_CONST_BITS); \
111  dst_m = __msa_pckev_h((v8i16) tp1_m, (v8i16) tp0_m); \
112  \
113  dst_m; \
114 } )
115 
116 #define VP9_ADST8(in0, in1, in2, in3, in4, in5, in6, in7, \
117  out0, out1, out2, out3, out4, out5, out6, out7) \
118 { \
119  v8i16 cnst0_m, cnst1_m, cnst2_m, cnst3_m, cnst4_m; \
120  v8i16 vec0_m, vec1_m, vec2_m, vec3_m, s0_m, s1_m; \
121  v8i16 coeff0_m = { cospi_2_64, cospi_6_64, cospi_10_64, cospi_14_64, \
122  cospi_18_64, cospi_22_64, cospi_26_64, cospi_30_64 }; \
123  v8i16 coeff1_m = { cospi_8_64, -cospi_8_64, cospi_16_64, \
124  -cospi_16_64, cospi_24_64, -cospi_24_64, 0, 0 }; \
125  \
126  SPLATI_H2_SH(coeff0_m, 0, 7, cnst0_m, cnst1_m); \
127  cnst2_m = -cnst0_m; \
128  ILVEV_H2_SH(cnst0_m, cnst1_m, cnst1_m, cnst2_m, cnst0_m, cnst1_m); \
129  SPLATI_H2_SH(coeff0_m, 4, 3, cnst2_m, cnst3_m); \
130  cnst4_m = -cnst2_m; \
131  ILVEV_H2_SH(cnst2_m, cnst3_m, cnst3_m, cnst4_m, cnst2_m, cnst3_m); \
132  \
133  ILVRL_H2_SH(in0, in7, vec1_m, vec0_m); \
134  ILVRL_H2_SH(in4, in3, vec3_m, vec2_m); \
135  VP9_DOT_ADD_SUB_SRARI_PCK(vec0_m, vec1_m, vec2_m, vec3_m, cnst0_m, \
136  cnst1_m, cnst2_m, cnst3_m, in7, in0, \
137  in4, in3); \
138  \
139  SPLATI_H2_SH(coeff0_m, 2, 5, cnst0_m, cnst1_m); \
140  cnst2_m = -cnst0_m; \
141  ILVEV_H2_SH(cnst0_m, cnst1_m, cnst1_m, cnst2_m, cnst0_m, cnst1_m); \
142  SPLATI_H2_SH(coeff0_m, 6, 1, cnst2_m, cnst3_m); \
143  cnst4_m = -cnst2_m; \
144  ILVEV_H2_SH(cnst2_m, cnst3_m, cnst3_m, cnst4_m, cnst2_m, cnst3_m); \
145  \
146  ILVRL_H2_SH(in2, in5, vec1_m, vec0_m); \
147  ILVRL_H2_SH(in6, in1, vec3_m, vec2_m); \
148  \
149  VP9_DOT_ADD_SUB_SRARI_PCK(vec0_m, vec1_m, vec2_m, vec3_m, cnst0_m, \
150  cnst1_m, cnst2_m, cnst3_m, in5, in2, \
151  in6, in1); \
152  BUTTERFLY_4(in7, in0, in2, in5, s1_m, s0_m, in2, in5); \
153  out7 = -s0_m; \
154  out0 = s1_m; \
155  \
156  SPLATI_H4_SH(coeff1_m, 0, 4, 1, 5, \
157  cnst0_m, cnst1_m, cnst2_m, cnst3_m); \
158  \
159  ILVEV_H2_SH(cnst3_m, cnst0_m, cnst1_m, cnst2_m, cnst3_m, cnst2_m); \
160  cnst0_m = __msa_ilvev_h(cnst1_m, cnst0_m); \
161  cnst1_m = cnst0_m; \
162  \
163  ILVRL_H2_SH(in4, in3, vec1_m, vec0_m); \
164  ILVRL_H2_SH(in6, in1, vec3_m, vec2_m); \
165  VP9_DOT_ADD_SUB_SRARI_PCK(vec0_m, vec1_m, vec2_m, vec3_m, cnst0_m, \
166  cnst2_m, cnst3_m, cnst1_m, out1, out6, \
167  s0_m, s1_m); \
168  \
169  SPLATI_H2_SH(coeff1_m, 2, 3, cnst0_m, cnst1_m); \
170  cnst1_m = __msa_ilvev_h(cnst1_m, cnst0_m); \
171  \
172  ILVRL_H2_SH(in2, in5, vec1_m, vec0_m); \
173  ILVRL_H2_SH(s0_m, s1_m, vec3_m, vec2_m); \
174  out3 = VP9_DOT_SHIFT_RIGHT_PCK_H(vec0_m, vec1_m, cnst0_m); \
175  out4 = VP9_DOT_SHIFT_RIGHT_PCK_H(vec0_m, vec1_m, cnst1_m); \
176  out2 = VP9_DOT_SHIFT_RIGHT_PCK_H(vec2_m, vec3_m, cnst0_m); \
177  out5 = VP9_DOT_SHIFT_RIGHT_PCK_H(vec2_m, vec3_m, cnst1_m); \
178  \
179  out1 = -out1; \
180  out3 = -out3; \
181  out5 = -out5; \
182 }
183 
184 #define VP9_MADD_SHORT(m0, m1, c0, c1, res0, res1) \
185 { \
186  v4i32 madd0_m, madd1_m, madd2_m, madd3_m; \
187  v8i16 madd_s0_m, madd_s1_m; \
188  \
189  ILVRL_H2_SH(m1, m0, madd_s0_m, madd_s1_m); \
190  DOTP_SH4_SW(madd_s0_m, madd_s1_m, madd_s0_m, madd_s1_m, \
191  c0, c0, c1, c1, madd0_m, madd1_m, madd2_m, madd3_m); \
192  SRARI_W4_SW(madd0_m, madd1_m, madd2_m, madd3_m, VP9_DCT_CONST_BITS); \
193  PCKEV_H2_SH(madd1_m, madd0_m, madd3_m, madd2_m, res0, res1); \
194 }
195 
196 #define VP9_MADD_BF(inp0, inp1, inp2, inp3, cst0, cst1, cst2, cst3, \
197  out0, out1, out2, out3) \
198 { \
199  v8i16 madd_s0_m, madd_s1_m, madd_s2_m, madd_s3_m; \
200  v4i32 tmp0_m, tmp1_m, tmp2_m, tmp3_m, m4_m, m5_m; \
201  \
202  ILVRL_H2_SH(inp1, inp0, madd_s0_m, madd_s1_m); \
203  ILVRL_H2_SH(inp3, inp2, madd_s2_m, madd_s3_m); \
204  DOTP_SH4_SW(madd_s0_m, madd_s1_m, madd_s2_m, madd_s3_m, \
205  cst0, cst0, cst2, cst2, tmp0_m, tmp1_m, tmp2_m, tmp3_m); \
206  BUTTERFLY_4(tmp0_m, tmp1_m, tmp3_m, tmp2_m, \
207  m4_m, m5_m, tmp3_m, tmp2_m); \
208  SRARI_W4_SW(m4_m, m5_m, tmp2_m, tmp3_m, VP9_DCT_CONST_BITS); \
209  PCKEV_H2_SH(m5_m, m4_m, tmp3_m, tmp2_m, out0, out1); \
210  DOTP_SH4_SW(madd_s0_m, madd_s1_m, madd_s2_m, madd_s3_m, \
211  cst1, cst1, cst3, cst3, tmp0_m, tmp1_m, tmp2_m, tmp3_m); \
212  BUTTERFLY_4(tmp0_m, tmp1_m, tmp3_m, tmp2_m, \
213  m4_m, m5_m, tmp3_m, tmp2_m); \
214  SRARI_W4_SW(m4_m, m5_m, tmp2_m, tmp3_m, VP9_DCT_CONST_BITS); \
215  PCKEV_H2_SH(m5_m, m4_m, tmp3_m, tmp2_m, out2, out3); \
216 }
217 
218 #define VP9_SET_COSPI_PAIR(c0_h, c1_h) \
219 ( { \
220  v8i16 out0_m, r0_m, r1_m; \
221  \
222  r0_m = __msa_fill_h(c0_h); \
223  r1_m = __msa_fill_h(c1_h); \
224  out0_m = __msa_ilvev_h(r1_m, r0_m); \
225  \
226  out0_m; \
227 } )
228 
229 #define VP9_ADDBLK_ST8x4_UB(dst, dst_stride, in0, in1, in2, in3) \
230 { \
231  uint8_t *dst_m = (uint8_t *) (dst); \
232  v16u8 dst0_m, dst1_m, dst2_m, dst3_m; \
233  v16i8 tmp0_m, tmp1_m; \
234  v16i8 zero_m = { 0 }; \
235  v8i16 res0_m, res1_m, res2_m, res3_m; \
236  \
237  LD_UB4(dst_m, dst_stride, dst0_m, dst1_m, dst2_m, dst3_m); \
238  ILVR_B4_SH(zero_m, dst0_m, zero_m, dst1_m, zero_m, dst2_m, \
239  zero_m, dst3_m, res0_m, res1_m, res2_m, res3_m); \
240  ADD4(res0_m, in0, res1_m, in1, res2_m, in2, res3_m, in3, \
241  res0_m, res1_m, res2_m, res3_m); \
242  CLIP_SH4_0_255(res0_m, res1_m, res2_m, res3_m); \
243  PCKEV_B2_SB(res1_m, res0_m, res3_m, res2_m, tmp0_m, tmp1_m); \
244  ST8x4_UB(tmp0_m, tmp1_m, dst_m, dst_stride); \
245 }
246 
247 #define VP9_IDCT4x4(in0, in1, in2, in3, out0, out1, out2, out3) \
248 { \
249  v8i16 c0_m, c1_m, c2_m, c3_m; \
250  v8i16 step0_m, step1_m; \
251  v4i32 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
252  \
253  c0_m = VP9_SET_COSPI_PAIR(cospi_16_64, cospi_16_64); \
254  c1_m = VP9_SET_COSPI_PAIR(cospi_16_64, -cospi_16_64); \
255  step0_m = __msa_ilvr_h(in2, in0); \
256  DOTP_SH2_SW(step0_m, step0_m, c0_m, c1_m, tmp0_m, tmp1_m); \
257  \
258  c2_m = VP9_SET_COSPI_PAIR(cospi_24_64, -cospi_8_64); \
259  c3_m = VP9_SET_COSPI_PAIR(cospi_8_64, cospi_24_64); \
260  step1_m = __msa_ilvr_h(in3, in1); \
261  DOTP_SH2_SW(step1_m, step1_m, c2_m, c3_m, tmp2_m, tmp3_m); \
262  SRARI_W4_SW(tmp0_m, tmp1_m, tmp2_m, tmp3_m, VP9_DCT_CONST_BITS); \
263  \
264  PCKEV_H2_SW(tmp1_m, tmp0_m, tmp3_m, tmp2_m, tmp0_m, tmp2_m); \
265  SLDI_B2_0_SW(tmp0_m, tmp2_m, tmp1_m, tmp3_m, 8); \
266  BUTTERFLY_4((v8i16) tmp0_m, (v8i16) tmp1_m, \
267  (v8i16) tmp2_m, (v8i16) tmp3_m, \
268  out0, out1, out2, out3); \
269 }
270 
271 #define VP9_IADST4x4(in0, in1, in2, in3, out0, out1, out2, out3) \
272 { \
273  v8i16 res0_m, res1_m, c0_m, c1_m; \
274  v8i16 k1_m, k2_m, k3_m, k4_m; \
275  v8i16 zero_m = { 0 }; \
276  v4i32 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
277  v4i32 int0_m, int1_m, int2_m, int3_m; \
278  v8i16 mask_m = { sinpi_1_9, sinpi_2_9, sinpi_3_9, \
279  sinpi_4_9, -sinpi_1_9, -sinpi_2_9, -sinpi_3_9, \
280  -sinpi_4_9 }; \
281  \
282  SPLATI_H4_SH(mask_m, 3, 0, 1, 2, c0_m, c1_m, k1_m, k2_m); \
283  ILVEV_H2_SH(c0_m, c1_m, k1_m, k2_m, c0_m, c1_m); \
284  ILVR_H2_SH(in0, in2, in1, in3, res0_m, res1_m); \
285  DOTP_SH2_SW(res0_m, res1_m, c0_m, c1_m, tmp2_m, tmp1_m); \
286  int0_m = tmp2_m + tmp1_m; \
287  \
288  SPLATI_H2_SH(mask_m, 4, 7, k4_m, k3_m); \
289  ILVEV_H2_SH(k4_m, k1_m, k3_m, k2_m, c0_m, c1_m); \
290  DOTP_SH2_SW(res0_m, res1_m, c0_m, c1_m, tmp0_m, tmp1_m); \
291  int1_m = tmp0_m + tmp1_m; \
292  \
293  c0_m = __msa_splati_h(mask_m, 6); \
294  ILVL_H2_SH(k2_m, c0_m, zero_m, k2_m, c0_m, c1_m); \
295  ILVR_H2_SH(in0, in2, in1, in3, res0_m, res1_m); \
296  DOTP_SH2_SW(res0_m, res1_m, c0_m, c1_m, tmp0_m, tmp1_m); \
297  int2_m = tmp0_m + tmp1_m; \
298  \
299  c0_m = __msa_splati_h(mask_m, 6); \
300  c0_m = __msa_ilvev_h(c0_m, k1_m); \
301  \
302  res0_m = __msa_ilvr_h((in1), (in3)); \
303  tmp0_m = __msa_dotp_s_w(res0_m, c0_m); \
304  int3_m = tmp2_m + tmp0_m; \
305  \
306  res0_m = __msa_ilvr_h((in2), (in3)); \
307  c1_m = __msa_ilvev_h(k4_m, k3_m); \
308  \
309  tmp2_m = __msa_dotp_s_w(res0_m, c1_m); \
310  res1_m = __msa_ilvr_h((in0), (in2)); \
311  c1_m = __msa_ilvev_h(k1_m, zero_m); \
312  \
313  tmp3_m = __msa_dotp_s_w(res1_m, c1_m); \
314  int3_m += tmp2_m; \
315  int3_m += tmp3_m; \
316  \
317  SRARI_W4_SW(int0_m, int1_m, int2_m, int3_m, VP9_DCT_CONST_BITS); \
318  PCKEV_H2_SH(int0_m, int0_m, int1_m, int1_m, out0, out1); \
319  PCKEV_H2_SH(int2_m, int2_m, int3_m, int3_m, out2, out3); \
320 }
321 
322 #define TRANSPOSE4X8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, \
323  out0, out1, out2, out3, out4, out5, out6, out7) \
324 { \
325  v8i16 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
326  v8i16 tmp0_n, tmp1_n, tmp2_n, tmp3_n; \
327  v8i16 zero_m = { 0 }; \
328  \
329  ILVR_H4_SH(in1, in0, in3, in2, in5, in4, in7, in6, \
330  tmp0_n, tmp1_n, tmp2_n, tmp3_n); \
331  ILVRL_W2_SH(tmp1_n, tmp0_n, tmp0_m, tmp2_m); \
332  ILVRL_W2_SH(tmp3_n, tmp2_n, tmp1_m, tmp3_m); \
333  \
334  out0 = (v8i16) __msa_ilvr_d((v2i64) tmp1_m, (v2i64) tmp0_m); \
335  out1 = (v8i16) __msa_ilvl_d((v2i64) tmp1_m, (v2i64) tmp0_m); \
336  out2 = (v8i16) __msa_ilvr_d((v2i64) tmp3_m, (v2i64) tmp2_m); \
337  out3 = (v8i16) __msa_ilvl_d((v2i64) tmp3_m, (v2i64) tmp2_m); \
338  \
339  out4 = zero_m; \
340  out5 = zero_m; \
341  out6 = zero_m; \
342  out7 = zero_m; \
343 }
344 
345 static void vp9_idct4x4_1_add_msa(int16_t *input, uint8_t *dst,
346  int32_t dst_stride)
347 {
348  int16_t out;
349  v8i16 vec;
350 
351  out = ROUND_POWER_OF_TWO((input[0] * cospi_16_64), VP9_DCT_CONST_BITS);
352  out = ROUND_POWER_OF_TWO((out * cospi_16_64), VP9_DCT_CONST_BITS);
353  out = ROUND_POWER_OF_TWO(out, 4);
354  vec = __msa_fill_h(out);
355 
356  ADDBLK_ST4x4_UB(vec, vec, vec, vec, dst, dst_stride);
357 }
358 
359 static void vp9_idct4x4_colcol_addblk_msa(int16_t *input, uint8_t *dst,
360  int32_t dst_stride)
361 {
362  v8i16 in0, in1, in2, in3;
363 
364  /* load vector elements of 4x4 block */
365  LD4x4_SH(input, in0, in1, in2, in3);
366  /* rows */
367  VP9_IDCT4x4(in0, in1, in2, in3, in0, in1, in2, in3);
368  /* columns */
369  TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
370  VP9_IDCT4x4(in0, in1, in2, in3, in0, in1, in2, in3);
371  /* rounding (add 2^3, divide by 2^4) */
372  SRARI_H4_SH(in0, in1, in2, in3, 4);
373  ADDBLK_ST4x4_UB(in0, in1, in2, in3, dst, dst_stride);
374 }
375 
376 static void vp9_iadst4x4_colcol_addblk_msa(int16_t *input, uint8_t *dst,
377  int32_t dst_stride)
378 {
379  v8i16 in0, in1, in2, in3;
380 
381  /* load vector elements of 4x4 block */
382  LD4x4_SH(input, in0, in1, in2, in3);
383  /* rows */
384  VP9_IADST4x4(in0, in1, in2, in3, in0, in1, in2, in3);
385  /* columns */
386  TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
387  VP9_IADST4x4(in0, in1, in2, in3, in0, in1, in2, in3);
388  /* rounding (add 2^3, divide by 2^4) */
389  SRARI_H4_SH(in0, in1, in2, in3, 4);
390  ADDBLK_ST4x4_UB(in0, in1, in2, in3, dst, dst_stride);
391 }
392 
393 static void vp9_iadst_idct_4x4_add_msa(int16_t *input, uint8_t *dst,
394  int32_t dst_stride, int32_t eob)
395 {
396  v8i16 in0, in1, in2, in3;
397 
398  /* load vector elements of 4x4 block */
399  LD4x4_SH(input, in0, in1, in2, in3);
400  /* cols */
401  VP9_IADST4x4(in0, in1, in2, in3, in0, in1, in2, in3);
402  /* columns */
403  TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
404  VP9_IDCT4x4(in0, in1, in2, in3, in0, in1, in2, in3);
405  /* rounding (add 2^3, divide by 2^4) */
406  SRARI_H4_SH(in0, in1, in2, in3, 4);
407  ADDBLK_ST4x4_UB(in0, in1, in2, in3, dst, dst_stride);
408 }
409 
410 static void vp9_idct_iadst_4x4_add_msa(int16_t *input, uint8_t *dst,
411  int32_t dst_stride, int32_t eob)
412 {
413  v8i16 in0, in1, in2, in3;
414 
415  /* load vector elements of 4x4 block */
416  LD4x4_SH(input, in0, in1, in2, in3);
417  /* cols */
418  VP9_IDCT4x4(in0, in1, in2, in3, in0, in1, in2, in3);
419  /* columns */
420  TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
421  VP9_IADST4x4(in0, in1, in2, in3, in0, in1, in2, in3);
422  /* rounding (add 2^3, divide by 2^4) */
423  SRARI_H4_SH(in0, in1, in2, in3, 4);
424  ADDBLK_ST4x4_UB(in0, in1, in2, in3, dst, dst_stride);
425 }
426 
427 #define VP9_SET_CONST_PAIR(mask_h, idx1_h, idx2_h) \
428 ( { \
429  v8i16 c0_m, c1_m; \
430  \
431  SPLATI_H2_SH(mask_h, idx1_h, idx2_h, c0_m, c1_m); \
432  c0_m = __msa_ilvev_h(c1_m, c0_m); \
433  \
434  c0_m; \
435 } )
436 
437 /* multiply and add macro */
438 #define VP9_MADD(inp0, inp1, inp2, inp3, cst0, cst1, cst2, cst3, \
439  out0, out1, out2, out3) \
440 { \
441  v8i16 madd_s0_m, madd_s1_m, madd_s2_m, madd_s3_m; \
442  v4i32 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
443  \
444  ILVRL_H2_SH(inp1, inp0, madd_s1_m, madd_s0_m); \
445  ILVRL_H2_SH(inp3, inp2, madd_s3_m, madd_s2_m); \
446  DOTP_SH4_SW(madd_s1_m, madd_s0_m, madd_s1_m, madd_s0_m, \
447  cst0, cst0, cst1, cst1, tmp0_m, tmp1_m, tmp2_m, tmp3_m); \
448  SRARI_W4_SW(tmp0_m, tmp1_m, tmp2_m, tmp3_m, VP9_DCT_CONST_BITS); \
449  PCKEV_H2_SH(tmp1_m, tmp0_m, tmp3_m, tmp2_m, out0, out1); \
450  DOTP_SH4_SW(madd_s3_m, madd_s2_m, madd_s3_m, madd_s2_m, \
451  cst2, cst2, cst3, cst3, tmp0_m, tmp1_m, tmp2_m, tmp3_m); \
452  SRARI_W4_SW(tmp0_m, tmp1_m, tmp2_m, tmp3_m, VP9_DCT_CONST_BITS); \
453  PCKEV_H2_SH(tmp1_m, tmp0_m, tmp3_m, tmp2_m, out2, out3); \
454 }
455 
456 /* idct 8x8 macro */
457 #define VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, \
458  out0, out1, out2, out3, out4, out5, out6, out7) \
459 { \
460  v8i16 tp0_m, tp1_m, tp2_m, tp3_m, tp4_m, tp5_m, tp6_m, tp7_m; \
461  v8i16 k0_m, k1_m, k2_m, k3_m, res0_m, res1_m, res2_m, res3_m; \
462  v4i32 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
463  v8i16 mask_m = { cospi_28_64, cospi_4_64, cospi_20_64, cospi_12_64, \
464  cospi_16_64, -cospi_4_64, -cospi_20_64, -cospi_16_64 }; \
465  \
466  k0_m = VP9_SET_CONST_PAIR(mask_m, 0, 5); \
467  k1_m = VP9_SET_CONST_PAIR(mask_m, 1, 0); \
468  k2_m = VP9_SET_CONST_PAIR(mask_m, 6, 3); \
469  k3_m = VP9_SET_CONST_PAIR(mask_m, 3, 2); \
470  VP9_MADD(in1, in7, in3, in5, k0_m, k1_m, k2_m, k3_m, in1, in7, in3, in5); \
471  SUB2(in1, in3, in7, in5, res0_m, res1_m); \
472  k0_m = VP9_SET_CONST_PAIR(mask_m, 4, 7); \
473  k1_m = __msa_splati_h(mask_m, 4); \
474  \
475  ILVRL_H2_SH(res0_m, res1_m, res2_m, res3_m); \
476  DOTP_SH4_SW(res2_m, res3_m, res2_m, res3_m, k0_m, k0_m, k1_m, k1_m, \
477  tmp0_m, tmp1_m, tmp2_m, tmp3_m); \
478  SRARI_W4_SW(tmp0_m, tmp1_m, tmp2_m, tmp3_m, VP9_DCT_CONST_BITS); \
479  tp4_m = in1 + in3; \
480  PCKEV_H2_SH(tmp1_m, tmp0_m, tmp3_m, tmp2_m, tp5_m, tp6_m); \
481  tp7_m = in7 + in5; \
482  k2_m = VP9_SET_COSPI_PAIR(cospi_24_64, -cospi_8_64); \
483  k3_m = VP9_SET_COSPI_PAIR(cospi_8_64, cospi_24_64); \
484  VP9_MADD(in0, in4, in2, in6, k1_m, k0_m, k2_m, k3_m, \
485  in0, in4, in2, in6); \
486  BUTTERFLY_4(in0, in4, in2, in6, tp0_m, tp1_m, tp2_m, tp3_m); \
487  BUTTERFLY_8(tp0_m, tp1_m, tp2_m, tp3_m, tp4_m, tp5_m, tp6_m, tp7_m, \
488  out0, out1, out2, out3, out4, out5, out6, out7); \
489 }
490 
491 #define VP9_IADST8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, \
492  out0, out1, out2, out3, out4, out5, out6, out7) \
493 { \
494  v4i32 r0_m, r1_m, r2_m, r3_m, r4_m, r5_m, r6_m, r7_m; \
495  v4i32 m0_m, m1_m, m2_m, m3_m, t0_m, t1_m; \
496  v8i16 res0_m, res1_m, res2_m, res3_m, k0_m, k1_m, in_s0, in_s1; \
497  v8i16 mask1_m = { cospi_2_64, cospi_30_64, -cospi_2_64, \
498  cospi_10_64, cospi_22_64, -cospi_10_64, cospi_18_64, cospi_14_64 }; \
499  v8i16 mask2_m = { cospi_14_64, -cospi_18_64, cospi_26_64, \
500  cospi_6_64, -cospi_26_64, cospi_8_64, cospi_24_64, -cospi_8_64 }; \
501  v8i16 mask3_m = { -cospi_24_64, cospi_8_64, cospi_16_64, \
502  -cospi_16_64, 0, 0, 0, 0 }; \
503  \
504  k0_m = VP9_SET_CONST_PAIR(mask1_m, 0, 1); \
505  k1_m = VP9_SET_CONST_PAIR(mask1_m, 1, 2); \
506  ILVRL_H2_SH(in1, in0, in_s1, in_s0); \
507  DOTP_SH4_SW(in_s1, in_s0, in_s1, in_s0, k0_m, k0_m, k1_m, k1_m, \
508  r0_m, r1_m, r2_m, r3_m); \
509  k0_m = VP9_SET_CONST_PAIR(mask1_m, 6, 7); \
510  k1_m = VP9_SET_CONST_PAIR(mask2_m, 0, 1); \
511  ILVRL_H2_SH(in5, in4, in_s1, in_s0); \
512  DOTP_SH4_SW(in_s1, in_s0, in_s1, in_s0, k0_m, k0_m, k1_m, k1_m, \
513  r4_m, r5_m, r6_m, r7_m); \
514  ADD4(r0_m, r4_m, r1_m, r5_m, r2_m, r6_m, r3_m, r7_m, \
515  m0_m, m1_m, m2_m, m3_m); \
516  SRARI_W4_SW(m0_m, m1_m, m2_m, m3_m, VP9_DCT_CONST_BITS); \
517  PCKEV_H2_SH(m1_m, m0_m, m3_m, m2_m, res0_m, res1_m); \
518  SUB4(r0_m, r4_m, r1_m, r5_m, r2_m, r6_m, r3_m, r7_m, \
519  m0_m, m1_m, m2_m, m3_m); \
520  SRARI_W4_SW(m0_m, m1_m, m2_m, m3_m, VP9_DCT_CONST_BITS); \
521  PCKEV_H2_SW(m1_m, m0_m, m3_m, m2_m, t0_m, t1_m); \
522  k0_m = VP9_SET_CONST_PAIR(mask1_m, 3, 4); \
523  k1_m = VP9_SET_CONST_PAIR(mask1_m, 4, 5); \
524  ILVRL_H2_SH(in3, in2, in_s1, in_s0); \
525  DOTP_SH4_SW(in_s1, in_s0, in_s1, in_s0, k0_m, k0_m, k1_m, k1_m, \
526  r0_m, r1_m, r2_m, r3_m); \
527  k0_m = VP9_SET_CONST_PAIR(mask2_m, 2, 3); \
528  k1_m = VP9_SET_CONST_PAIR(mask2_m, 3, 4); \
529  ILVRL_H2_SH(in7, in6, in_s1, in_s0); \
530  DOTP_SH4_SW(in_s1, in_s0, in_s1, in_s0, k0_m, k0_m, k1_m, k1_m, \
531  r4_m, r5_m, r6_m, r7_m); \
532  ADD4(r0_m, r4_m, r1_m, r5_m, r2_m, r6_m, r3_m, r7_m, \
533  m0_m, m1_m, m2_m, m3_m); \
534  SRARI_W4_SW(m0_m, m1_m, m2_m, m3_m, VP9_DCT_CONST_BITS); \
535  PCKEV_H2_SH(m1_m, m0_m, m3_m, m2_m, res2_m, res3_m); \
536  SUB4(r0_m, r4_m, r1_m, r5_m, r2_m, r6_m, r3_m, r7_m, \
537  m0_m, m1_m, m2_m, m3_m); \
538  SRARI_W4_SW(m0_m, m1_m, m2_m, m3_m, VP9_DCT_CONST_BITS); \
539  PCKEV_H2_SW(m1_m, m0_m, m3_m, m2_m, r2_m, r3_m); \
540  ILVRL_H2_SW(r3_m, r2_m, m2_m, m3_m); \
541  BUTTERFLY_4(res0_m, res1_m, res3_m, res2_m, out0, in7, in4, in3); \
542  k0_m = VP9_SET_CONST_PAIR(mask2_m, 5, 6); \
543  k1_m = VP9_SET_CONST_PAIR(mask2_m, 6, 7); \
544  ILVRL_H2_SH(t1_m, t0_m, in_s1, in_s0); \
545  DOTP_SH4_SW(in_s1, in_s0, in_s1, in_s0, k0_m, k0_m, k1_m, k1_m, \
546  r0_m, r1_m, r2_m, r3_m); \
547  k1_m = VP9_SET_CONST_PAIR(mask3_m, 0, 1); \
548  DOTP_SH4_SW(m2_m, m3_m, m2_m, m3_m, k0_m, k0_m, k1_m, k1_m, \
549  r4_m, r5_m, r6_m, r7_m); \
550  ADD4(r0_m, r6_m, r1_m, r7_m, r2_m, r4_m, r3_m, r5_m, \
551  m0_m, m1_m, m2_m, m3_m); \
552  SRARI_W4_SW(m0_m, m1_m, m2_m, m3_m, VP9_DCT_CONST_BITS); \
553  PCKEV_H2_SH(m1_m, m0_m, m3_m, m2_m, in1, out6); \
554  SUB4(r0_m, r6_m, r1_m, r7_m, r2_m, r4_m, r3_m, r5_m, \
555  m0_m, m1_m, m2_m, m3_m); \
556  SRARI_W4_SW(m0_m, m1_m, m2_m, m3_m, VP9_DCT_CONST_BITS); \
557  PCKEV_H2_SH(m1_m, m0_m, m3_m, m2_m, in2, in5); \
558  k0_m = VP9_SET_CONST_PAIR(mask3_m, 2, 2); \
559  k1_m = VP9_SET_CONST_PAIR(mask3_m, 2, 3); \
560  ILVRL_H2_SH(in4, in3, in_s1, in_s0); \
561  DOTP_SH4_SW(in_s1, in_s0, in_s1, in_s0, k0_m, k0_m, k1_m, k1_m, \
562  m0_m, m1_m, m2_m, m3_m); \
563  SRARI_W4_SW(m0_m, m1_m, m2_m, m3_m, VP9_DCT_CONST_BITS); \
564  PCKEV_H2_SH(m1_m, m0_m, m3_m, m2_m, in3, out4); \
565  ILVRL_H2_SW(in5, in2, m2_m, m3_m); \
566  DOTP_SH4_SW(m2_m, m3_m, m2_m, m3_m, k0_m, k0_m, k1_m, k1_m, \
567  m0_m, m1_m, m2_m, m3_m); \
568  SRARI_W4_SW(m0_m, m1_m, m2_m, m3_m, VP9_DCT_CONST_BITS); \
569  PCKEV_H2_SH(m1_m, m0_m, m3_m, m2_m, out2, in5); \
570  \
571  out1 = -in1; \
572  out3 = -in3; \
573  out5 = -in5; \
574  out7 = -in7; \
575 }
576 
577 static void vp9_idct8x8_1_add_msa(int16_t *input, uint8_t *dst,
578  int32_t dst_stride)
579 {
580  int16_t out;
581  int32_t val;
582  v8i16 vec;
583 
584  out = ROUND_POWER_OF_TWO((input[0] * cospi_16_64), VP9_DCT_CONST_BITS);
585  out = ROUND_POWER_OF_TWO((out * cospi_16_64), VP9_DCT_CONST_BITS);
586  val = ROUND_POWER_OF_TWO(out, 5);
587  vec = __msa_fill_h(val);
588 
589  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, vec, vec, vec, vec);
590  dst += (4 * dst_stride);
591  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, vec, vec, vec, vec);
592 }
593 
594 static void vp9_idct8x8_12_colcol_addblk_msa(int16_t *input, uint8_t *dst,
595  int32_t dst_stride)
596 {
597  v8i16 in0, in1, in2, in3, in4, in5, in6, in7;
598  v8i16 s0, s1, s2, s3, s4, s5, s6, s7, k0, k1, k2, k3, m0, m1, m2, m3;
599  v4i32 tmp0, tmp1, tmp2, tmp3;
600  v8i16 zero = { 0 };
601 
602  /* load vector elements of 8x8 block */
603  LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7);
604  ILVR_D2_SH(in1, in0, in3, in2, in0, in1);
605  ILVR_D2_SH(in5, in4, in7, in6, in2, in3);
606  //TRANSPOSE8X4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
607 
608  /* stage1 */
609  ILVL_H2_SH(in3, in0, in2, in1, s0, s1);
610  k0 = VP9_SET_COSPI_PAIR(cospi_28_64, -cospi_4_64);
611  k1 = VP9_SET_COSPI_PAIR(cospi_4_64, cospi_28_64);
612  k2 = VP9_SET_COSPI_PAIR(-cospi_20_64, cospi_12_64);
613  k3 = VP9_SET_COSPI_PAIR(cospi_12_64, cospi_20_64);
614  DOTP_SH4_SW(s0, s0, s1, s1, k0, k1, k2, k3, tmp0, tmp1, tmp2, tmp3);
615  SRARI_W4_SW(tmp0, tmp1, tmp2, tmp3, VP9_DCT_CONST_BITS);
616  PCKEV_H2_SH(zero, tmp0, zero, tmp1, s0, s1);
617  PCKEV_H2_SH(zero, tmp2, zero, tmp3, s2, s3);
618  BUTTERFLY_4(s0, s1, s3, s2, s4, s7, s6, s5);
619 
620  /* stage2 */
621  ILVR_H2_SH(in3, in1, in2, in0, s1, s0);
622  k0 = VP9_SET_COSPI_PAIR(cospi_16_64, cospi_16_64);
623  k1 = VP9_SET_COSPI_PAIR(cospi_16_64, -cospi_16_64);
624  k2 = VP9_SET_COSPI_PAIR(cospi_24_64, -cospi_8_64);
625  k3 = VP9_SET_COSPI_PAIR(cospi_8_64, cospi_24_64);
626  DOTP_SH4_SW(s0, s0, s1, s1, k0, k1, k2, k3, tmp0, tmp1, tmp2, tmp3);
627  SRARI_W4_SW(tmp0, tmp1, tmp2, tmp3, VP9_DCT_CONST_BITS);
628  PCKEV_H2_SH(zero, tmp0, zero, tmp1, s0, s1);
629  PCKEV_H2_SH(zero, tmp2, zero, tmp3, s2, s3);
630  BUTTERFLY_4(s0, s1, s2, s3, m0, m1, m2, m3);
631 
632  /* stage3 */
633  s0 = __msa_ilvr_h(s6, s5);
634 
635  k1 = VP9_SET_COSPI_PAIR(-cospi_16_64, cospi_16_64);
636  DOTP_SH2_SW(s0, s0, k1, k0, tmp0, tmp1);
637  SRARI_W2_SW(tmp0, tmp1, VP9_DCT_CONST_BITS);
638  PCKEV_H2_SH(zero, tmp0, zero, tmp1, s2, s3);
639 
640  /* stage4 */
641  BUTTERFLY_8(m0, m1, m2, m3, s4, s2, s3, s7,
642  in0, in1, in2, in3, in4, in5, in6, in7);
643  TRANSPOSE4X8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7,
644  in0, in1, in2, in3, in4, in5, in6, in7);
645  VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7,
646  in0, in1, in2, in3, in4, in5, in6, in7);
647 
648  /* final rounding (add 2^4, divide by 2^5) and shift */
649  SRARI_H4_SH(in0, in1, in2, in3, 5);
650  SRARI_H4_SH(in4, in5, in6, in7, 5);
651 
652  /* add block and store 8x8 */
653  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, in0, in1, in2, in3);
654  dst += (4 * dst_stride);
655  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, in4, in5, in6, in7);
656 }
657 
658 static void vp9_idct8x8_colcol_addblk_msa(int16_t *input, uint8_t *dst,
659  int32_t dst_stride)
660 {
661  v8i16 in0, in1, in2, in3, in4, in5, in6, in7;
662 
663  /* load vector elements of 8x8 block */
664  LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7);
665  /* 1D idct8x8 */
666  VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7,
667  in0, in1, in2, in3, in4, in5, in6, in7);
668  /* columns transform */
669  TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7,
670  in0, in1, in2, in3, in4, in5, in6, in7);
671  /* 1D idct8x8 */
672  VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7,
673  in0, in1, in2, in3, in4, in5, in6, in7);
674  /* final rounding (add 2^4, divide by 2^5) and shift */
675  SRARI_H4_SH(in0, in1, in2, in3, 5);
676  SRARI_H4_SH(in4, in5, in6, in7, 5);
677  /* add block and store 8x8 */
678  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, in0, in1, in2, in3);
679  dst += (4 * dst_stride);
680  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, in4, in5, in6, in7);
681 }
682 
683 static void vp9_iadst8x8_colcol_addblk_msa(int16_t *input, uint8_t *dst,
684  int32_t dst_stride)
685 {
686  v8i16 in0, in1, in2, in3, in4, in5, in6, in7;
687  v8i16 res0, res1, res2, res3, res4, res5, res6, res7;
688  v16u8 dst0, dst1, dst2, dst3, dst4, dst5, dst6, dst7;
689  v8i16 out0, out1, out2, out3, out4, out5, out6, out7;
690  v8i16 cnst0, cnst1, cnst2, cnst3, cnst4;
691  v8i16 temp0, temp1, temp2, temp3, s0, s1;
692  v16i8 zero = { 0 };
693 
694  /* load vector elements of 8x8 block */
695  LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7);
696 
697  /* 1D adst8x8 */
698  VP9_ADST8(in0, in1, in2, in3, in4, in5, in6, in7,
699  in0, in1, in2, in3, in4, in5, in6, in7);
700 
701  /* columns transform */
702  TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7,
703  in0, in1, in2, in3, in4, in5, in6, in7);
704 
705  cnst0 = __msa_fill_h(cospi_2_64);
706  cnst1 = __msa_fill_h(cospi_30_64);
707  cnst2 = -cnst0;
708  ILVEV_H2_SH(cnst0, cnst1, cnst1, cnst2, cnst0, cnst1);
709  cnst2 = __msa_fill_h(cospi_18_64);
710  cnst3 = __msa_fill_h(cospi_14_64);
711  cnst4 = -cnst2;
712  ILVEV_H2_SH(cnst2, cnst3, cnst3, cnst4, cnst2, cnst3);
713 
714  ILVRL_H2_SH(in0, in7, temp1, temp0);
715  ILVRL_H2_SH(in4, in3, temp3, temp2);
716  VP9_DOT_ADD_SUB_SRARI_PCK(temp0, temp1, temp2, temp3, cnst0, cnst1, cnst2,
717  cnst3, in7, in0, in4, in3);
718 
719  cnst0 = __msa_fill_h(cospi_10_64);
720  cnst1 = __msa_fill_h(cospi_22_64);
721  cnst2 = -cnst0;
722  ILVEV_H2_SH(cnst0, cnst1, cnst1, cnst2, cnst0, cnst1);
723  cnst2 = __msa_fill_h(cospi_26_64);
724  cnst3 = __msa_fill_h(cospi_6_64);
725  cnst4 = -cnst2;
726  ILVEV_H2_SH(cnst2, cnst3, cnst3, cnst4, cnst2, cnst3);
727 
728  ILVRL_H2_SH(in2, in5, temp1, temp0);
729  ILVRL_H2_SH(in6, in1, temp3, temp2);
730  VP9_DOT_ADD_SUB_SRARI_PCK(temp0, temp1, temp2, temp3, cnst0, cnst1, cnst2,
731  cnst3, in5, in2, in6, in1);
732  BUTTERFLY_4(in7, in0, in2, in5, s1, s0, in2, in5);
733  out7 = -s0;
734  out0 = s1;
735  SRARI_H2_SH(out0, out7, 5);
736  dst0 = LD_UB(dst + 0 * dst_stride);
737  dst7 = LD_UB(dst + 7 * dst_stride);
738 
739  res0 = (v8i16) __msa_ilvr_b(zero, (v16i8) dst0);
740  res0 += out0;
741  res0 = CLIP_SH_0_255(res0);
742  res0 = (v8i16) __msa_pckev_b((v16i8) res0, (v16i8) res0);
743  ST8x1_UB(res0, dst);
744 
745  res7 = (v8i16) __msa_ilvr_b(zero, (v16i8) dst7);
746  res7 += out7;
747  res7 = CLIP_SH_0_255(res7);
748  res7 = (v8i16) __msa_pckev_b((v16i8) res7, (v16i8) res7);
749  ST8x1_UB(res7, dst + 7 * dst_stride);
750 
751  cnst1 = __msa_fill_h(cospi_24_64);
752  cnst0 = __msa_fill_h(cospi_8_64);
753  cnst3 = -cnst1;
754  cnst2 = -cnst0;
755 
756  ILVEV_H2_SH(cnst3, cnst0, cnst1, cnst2, cnst3, cnst2);
757  cnst0 = __msa_ilvev_h(cnst1, cnst0);
758  cnst1 = cnst0;
759 
760  ILVRL_H2_SH(in4, in3, temp1, temp0);
761  ILVRL_H2_SH(in6, in1, temp3, temp2);
762  VP9_DOT_ADD_SUB_SRARI_PCK(temp0, temp1, temp2, temp3, cnst0, cnst2, cnst3,
763  cnst1, out1, out6, s0, s1);
764  out1 = -out1;
765  SRARI_H2_SH(out1, out6, 5);
766  dst1 = LD_UB(dst + 1 * dst_stride);
767  dst6 = LD_UB(dst + 6 * dst_stride);
768  ILVR_B2_SH(zero, dst1, zero, dst6, res1, res6);
769  ADD2(res1, out1, res6, out6, res1, res6);
770  CLIP_SH2_0_255(res1, res6);
771  PCKEV_B2_SH(res1, res1, res6, res6, res1, res6);
772  ST8x1_UB(res1, dst + dst_stride);
773  ST8x1_UB(res6, dst + 6 * dst_stride);
774 
775  cnst0 = __msa_fill_h(cospi_16_64);
776  cnst1 = -cnst0;
777  cnst1 = __msa_ilvev_h(cnst1, cnst0);
778 
779  ILVRL_H2_SH(in2, in5, temp1, temp0);
780  ILVRL_H2_SH(s0, s1, temp3, temp2);
781  out3 = VP9_DOT_SHIFT_RIGHT_PCK_H(temp0, temp1, cnst0);
782  out4 = VP9_DOT_SHIFT_RIGHT_PCK_H(temp0, temp1, cnst1);
783  out3 = -out3;
784  SRARI_H2_SH(out3, out4, 5);
785  dst3 = LD_UB(dst + 3 * dst_stride);
786  dst4 = LD_UB(dst + 4 * dst_stride);
787  ILVR_B2_SH(zero, dst3, zero, dst4, res3, res4);
788  ADD2(res3, out3, res4, out4, res3, res4);
789  CLIP_SH2_0_255(res3, res4);
790  PCKEV_B2_SH(res3, res3, res4, res4, res3, res4);
791  ST8x1_UB(res3, dst + 3 * dst_stride);
792  ST8x1_UB(res4, dst + 4 * dst_stride);
793 
794  out2 = VP9_DOT_SHIFT_RIGHT_PCK_H(temp2, temp3, cnst0);
795  out5 = VP9_DOT_SHIFT_RIGHT_PCK_H(temp2, temp3, cnst1);
796  out5 = -out5;
797  SRARI_H2_SH(out2, out5, 5);
798  dst2 = LD_UB(dst + 2 * dst_stride);
799  dst5 = LD_UB(dst + 5 * dst_stride);
800  ILVR_B2_SH(zero, dst2, zero, dst5, res2, res5);
801  ADD2(res2, out2, res5, out5, res2, res5);
802  CLIP_SH2_0_255(res2, res5);
803  PCKEV_B2_SH(res2, res2, res5, res5, res2, res5);
804  ST8x1_UB(res2, dst + 2 * dst_stride);
805  ST8x1_UB(res5, dst + 5 * dst_stride);
806 }
807 
808 static void vp9_iadst_idct_8x8_add_msa(int16_t *input, uint8_t *dst,
809  int32_t dst_stride, int32_t eob)
810 {
811  v8i16 in0, in1, in2, in3, in4, in5, in6, in7;
812 
813  /* load vector elements of 8x8 block */
814  LD_SH8(input, 8, in1, in6, in3, in4, in5, in2, in7, in0);
815  /* 1D idct8x8 */
816  VP9_IADST8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7,
817  in0, in1, in2, in3, in4, in5, in6, in7);
818  /* columns transform */
819  TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7,
820  in0, in1, in2, in3, in4, in5, in6, in7);
821  /* 1D idct8x8 */
822  VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7,
823  in0, in1, in2, in3, in4, in5, in6, in7);
824  /* final rounding (add 2^4, divide by 2^5) and shift */
825  SRARI_H4_SH(in0, in1, in2, in3, 5);
826  SRARI_H4_SH(in4, in5, in6, in7, 5);
827  /* add block and store 8x8 */
828  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, in0, in1, in2, in3);
829  dst += (4 * dst_stride);
830  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, in4, in5, in6, in7);
831 }
832 
833 static void vp9_idct_iadst_8x8_add_msa(int16_t *input, uint8_t *dst,
834  int32_t dst_stride, int32_t eob)
835 {
836  v8i16 in0, in1, in2, in3, in4, in5, in6, in7;
837 
838  /* load vector elements of 8x8 block */
839  LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7);
840 
841  /* 1D idct8x8 */
842  VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7,
843  in0, in1, in2, in3, in4, in5, in6, in7);
844  /* columns transform */
845  TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7,
846  in1, in6, in3, in4, in5, in2, in7, in0);
847  /* 1D idct8x8 */
848  VP9_IADST8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7,
849  in0, in1, in2, in3, in4, in5, in6, in7);
850  /* final rounding (add 2^4, divide by 2^5) and shift */
851  SRARI_H4_SH(in0, in1, in2, in3, 5);
852  SRARI_H4_SH(in4, in5, in6, in7, 5);
853  /* add block and store 8x8 */
854  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, in0, in1, in2, in3);
855  dst += (4 * dst_stride);
856  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, in4, in5, in6, in7);
857 }
858 
859 #define VP9_IADST8x16_1D(r0, r1, r2, r3, r4, r5, r6, r7, r8, \
860  r9, r10, r11, r12, r13, r14, r15, \
861  out0, out1, out2, out3, out4, out5, \
862  out6, out7, out8, out9, out10, out11, \
863  out12, out13, out14, out15) \
864 { \
865  v8i16 g0_m, g1_m, g2_m, g3_m, g4_m, g5_m, g6_m, g7_m; \
866  v8i16 g8_m, g9_m, g10_m, g11_m, g12_m, g13_m, g14_m, g15_m; \
867  v8i16 h0_m, h1_m, h2_m, h3_m, h4_m, h5_m, h6_m, h7_m; \
868  v8i16 h8_m, h9_m, h10_m, h11_m; \
869  v8i16 k0_m, k1_m, k2_m, k3_m; \
870  \
871  /* stage 1 */ \
872  k0_m = VP9_SET_COSPI_PAIR(cospi_1_64, cospi_31_64); \
873  k1_m = VP9_SET_COSPI_PAIR(cospi_31_64, -cospi_1_64); \
874  k2_m = VP9_SET_COSPI_PAIR(cospi_17_64, cospi_15_64); \
875  k3_m = VP9_SET_COSPI_PAIR(cospi_15_64, -cospi_17_64); \
876  VP9_MADD_BF(r15, r0, r7, r8, k0_m, k1_m, k2_m, k3_m, \
877  g0_m, g1_m, g2_m, g3_m); \
878  k0_m = VP9_SET_COSPI_PAIR(cospi_5_64, cospi_27_64); \
879  k1_m = VP9_SET_COSPI_PAIR(cospi_27_64, -cospi_5_64); \
880  k2_m = VP9_SET_COSPI_PAIR(cospi_21_64, cospi_11_64); \
881  k3_m = VP9_SET_COSPI_PAIR(cospi_11_64, -cospi_21_64); \
882  VP9_MADD_BF(r13, r2, r5, r10, k0_m, k1_m, k2_m, k3_m, \
883  g4_m, g5_m, g6_m, g7_m); \
884  k0_m = VP9_SET_COSPI_PAIR(cospi_9_64, cospi_23_64); \
885  k1_m = VP9_SET_COSPI_PAIR(cospi_23_64, -cospi_9_64); \
886  k2_m = VP9_SET_COSPI_PAIR(cospi_25_64, cospi_7_64); \
887  k3_m = VP9_SET_COSPI_PAIR(cospi_7_64, -cospi_25_64); \
888  VP9_MADD_BF(r11, r4, r3, r12, k0_m, k1_m, k2_m, k3_m, \
889  g8_m, g9_m, g10_m, g11_m); \
890  k0_m = VP9_SET_COSPI_PAIR(cospi_13_64, cospi_19_64); \
891  k1_m = VP9_SET_COSPI_PAIR(cospi_19_64, -cospi_13_64); \
892  k2_m = VP9_SET_COSPI_PAIR(cospi_29_64, cospi_3_64); \
893  k3_m = VP9_SET_COSPI_PAIR(cospi_3_64, -cospi_29_64); \
894  VP9_MADD_BF(r9, r6, r1, r14, k0_m, k1_m, k2_m, k3_m, \
895  g12_m, g13_m, g14_m, g15_m); \
896  \
897  /* stage 2 */ \
898  k0_m = VP9_SET_COSPI_PAIR(cospi_4_64, cospi_28_64); \
899  k1_m = VP9_SET_COSPI_PAIR(cospi_28_64, -cospi_4_64); \
900  k2_m = VP9_SET_COSPI_PAIR(-cospi_28_64, cospi_4_64); \
901  VP9_MADD_BF(g1_m, g3_m, g9_m, g11_m, k0_m, k1_m, k2_m, k0_m, \
902  h0_m, h1_m, h2_m, h3_m); \
903  k0_m = VP9_SET_COSPI_PAIR(cospi_12_64, cospi_20_64); \
904  k1_m = VP9_SET_COSPI_PAIR(-cospi_20_64, cospi_12_64); \
905  k2_m = VP9_SET_COSPI_PAIR(cospi_20_64, -cospi_12_64); \
906  VP9_MADD_BF(g7_m, g5_m, g15_m, g13_m, k0_m, k1_m, k2_m, k0_m, \
907  h4_m, h5_m, h6_m, h7_m); \
908  BUTTERFLY_4(h0_m, h2_m, h6_m, h4_m, out8, out9, out11, out10); \
909  BUTTERFLY_8(g0_m, g2_m, g4_m, g6_m, g14_m, g12_m, g10_m, g8_m, \
910  h8_m, h9_m, h10_m, h11_m, h6_m, h4_m, h2_m, h0_m); \
911  \
912  /* stage 3 */ \
913  BUTTERFLY_4(h8_m, h9_m, h11_m, h10_m, out0, out1, h11_m, h10_m); \
914  k0_m = VP9_SET_COSPI_PAIR(cospi_8_64, cospi_24_64); \
915  k1_m = VP9_SET_COSPI_PAIR(cospi_24_64, -cospi_8_64); \
916  k2_m = VP9_SET_COSPI_PAIR(-cospi_24_64, cospi_8_64); \
917  VP9_MADD_BF(h0_m, h2_m, h4_m, h6_m, k0_m, k1_m, k2_m, k0_m, \
918  out4, out6, out5, out7); \
919  VP9_MADD_BF(h1_m, h3_m, h5_m, h7_m, k0_m, k1_m, k2_m, k0_m, \
920  out12, out14, out13, out15); \
921  \
922  /* stage 4 */ \
923  k0_m = VP9_SET_COSPI_PAIR(cospi_16_64, cospi_16_64); \
924  k1_m = VP9_SET_COSPI_PAIR(-cospi_16_64, -cospi_16_64); \
925  k2_m = VP9_SET_COSPI_PAIR(cospi_16_64, -cospi_16_64); \
926  k3_m = VP9_SET_COSPI_PAIR(-cospi_16_64, cospi_16_64); \
927  VP9_MADD_SHORT(h10_m, h11_m, k1_m, k2_m, out2, out3); \
928  VP9_MADD_SHORT(out6, out7, k0_m, k3_m, out6, out7); \
929  VP9_MADD_SHORT(out10, out11, k0_m, k3_m, out10, out11); \
930  VP9_MADD_SHORT(out14, out15, k1_m, k2_m, out14, out15); \
931 }
932 
933 static void vp9_idct16_1d_columns_addblk_msa(int16_t *input, uint8_t *dst,
934  int32_t dst_stride)
935 {
936  v8i16 loc0, loc1, loc2, loc3;
937  v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14;
938  v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15;
939  v8i16 tmp5, tmp6, tmp7;
940 
941  /* load up 8x8 */
942  LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
943  input += 8 * 16;
944  /* load bottom 8x8 */
945  LD_SH8(input, 16, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15);
946 
947  VP9_DOTP_CONST_PAIR(reg2, reg14, cospi_28_64, cospi_4_64, reg2, reg14);
948  VP9_DOTP_CONST_PAIR(reg10, reg6, cospi_12_64, cospi_20_64, reg10, reg6);
949  BUTTERFLY_4(reg2, reg14, reg6, reg10, loc0, loc1, reg14, reg2);
950  VP9_DOTP_CONST_PAIR(reg14, reg2, cospi_16_64, cospi_16_64, loc2, loc3);
951  VP9_DOTP_CONST_PAIR(reg0, reg8, cospi_16_64, cospi_16_64, reg0, reg8);
952  VP9_DOTP_CONST_PAIR(reg4, reg12, cospi_24_64, cospi_8_64, reg4, reg12);
953  BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14);
954 
955  reg0 = reg2 - loc1;
956  reg2 = reg2 + loc1;
957  reg12 = reg14 - loc0;
958  reg14 = reg14 + loc0;
959  reg4 = reg6 - loc3;
960  reg6 = reg6 + loc3;
961  reg8 = reg10 - loc2;
962  reg10 = reg10 + loc2;
963 
964  /* stage 2 */
965  VP9_DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15);
966  VP9_DOTP_CONST_PAIR(reg9, reg7, cospi_14_64, cospi_18_64, loc2, loc3);
967 
968  reg9 = reg1 - loc2;
969  reg1 = reg1 + loc2;
970  reg7 = reg15 - loc3;
971  reg15 = reg15 + loc3;
972 
973  VP9_DOTP_CONST_PAIR(reg5, reg11, cospi_22_64, cospi_10_64, reg5, reg11);
974  VP9_DOTP_CONST_PAIR(reg13, reg3, cospi_6_64, cospi_26_64, loc0, loc1);
975  BUTTERFLY_4(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5);
976 
977  loc1 = reg15 + reg3;
978  reg3 = reg15 - reg3;
979  loc2 = reg2 + loc1;
980  reg15 = reg2 - loc1;
981 
982  loc1 = reg1 + reg13;
983  reg13 = reg1 - reg13;
984  loc0 = reg0 + loc1;
985  loc1 = reg0 - loc1;
986  tmp6 = loc0;
987  tmp7 = loc1;
988  reg0 = loc2;
989 
990  VP9_DOTP_CONST_PAIR(reg7, reg9, cospi_24_64, cospi_8_64, reg7, reg9);
991  VP9_DOTP_CONST_PAIR((-reg5), (-reg11), cospi_8_64, cospi_24_64, reg5,
992  reg11);
993 
994  loc0 = reg9 + reg5;
995  reg5 = reg9 - reg5;
996  reg2 = reg6 + loc0;
997  reg1 = reg6 - loc0;
998 
999  loc0 = reg7 + reg11;
1000  reg11 = reg7 - reg11;
1001  loc1 = reg4 + loc0;
1002  loc2 = reg4 - loc0;
1003  tmp5 = loc1;
1004 
1005  VP9_DOTP_CONST_PAIR(reg5, reg11, cospi_16_64, cospi_16_64, reg5, reg11);
1006  BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1);
1007 
1008  reg10 = loc0;
1009  reg11 = loc1;
1010 
1011  VP9_DOTP_CONST_PAIR(reg3, reg13, cospi_16_64, cospi_16_64, reg3, reg13);
1012  BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5);
1013  reg13 = loc2;
1014 
1015  /* Transpose and store the output */
1016  reg12 = tmp5;
1017  reg14 = tmp6;
1018  reg3 = tmp7;
1019 
1020  SRARI_H4_SH(reg0, reg2, reg4, reg6, 6);
1021  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, reg0, reg2, reg4, reg6);
1022  dst += (4 * dst_stride);
1023  SRARI_H4_SH(reg8, reg10, reg12, reg14, 6);
1024  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, reg8, reg10, reg12, reg14);
1025  dst += (4 * dst_stride);
1026  SRARI_H4_SH(reg3, reg13, reg11, reg5, 6);
1027  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, reg3, reg13, reg11, reg5);
1028  dst += (4 * dst_stride);
1029  SRARI_H4_SH(reg7, reg9, reg1, reg15, 6);
1030  VP9_ADDBLK_ST8x4_UB(dst, dst_stride, reg7, reg9, reg1, reg15);
1031 }
1032 
1033 static void vp9_idct16_1d_columns_msa(int16_t *input, int16_t *output)
1034 {
1035  v8i16 loc0, loc1, loc2, loc3;
1036  v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14;
1037  v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15;
1038  v8i16 tmp5, tmp6, tmp7;
1039 
1040  /* load up 8x8 */
1041  LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
1042  input += 8 * 16;
1043  /* load bottom 8x8 */
1044  LD_SH8(input, 16, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15);
1045 
1046  VP9_DOTP_CONST_PAIR(reg2, reg14, cospi_28_64, cospi_4_64, reg2, reg14);
1047  VP9_DOTP_CONST_PAIR(reg10, reg6, cospi_12_64, cospi_20_64, reg10, reg6);
1048  BUTTERFLY_4(reg2, reg14, reg6, reg10, loc0, loc1, reg14, reg2);
1049  VP9_DOTP_CONST_PAIR(reg14, reg2, cospi_16_64, cospi_16_64, loc2, loc3);
1050  VP9_DOTP_CONST_PAIR(reg0, reg8, cospi_16_64, cospi_16_64, reg0, reg8);
1051  VP9_DOTP_CONST_PAIR(reg4, reg12, cospi_24_64, cospi_8_64, reg4, reg12);
1052  BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14);
1053 
1054  reg0 = reg2 - loc1;
1055  reg2 = reg2 + loc1;
1056  reg12 = reg14 - loc0;
1057  reg14 = reg14 + loc0;
1058  reg4 = reg6 - loc3;
1059  reg6 = reg6 + loc3;
1060  reg8 = reg10 - loc2;
1061  reg10 = reg10 + loc2;
1062 
1063  /* stage 2 */
1064  VP9_DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15);
1065  VP9_DOTP_CONST_PAIR(reg9, reg7, cospi_14_64, cospi_18_64, loc2, loc3);
1066 
1067  reg9 = reg1 - loc2;
1068  reg1 = reg1 + loc2;
1069  reg7 = reg15 - loc3;
1070  reg15 = reg15 + loc3;
1071 
1072  VP9_DOTP_CONST_PAIR(reg5, reg11, cospi_22_64, cospi_10_64, reg5, reg11);
1073  VP9_DOTP_CONST_PAIR(reg13, reg3, cospi_6_64, cospi_26_64, loc0, loc1);
1074  BUTTERFLY_4(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5);
1075 
1076  loc1 = reg15 + reg3;
1077  reg3 = reg15 - reg3;
1078  loc2 = reg2 + loc1;
1079  reg15 = reg2 - loc1;
1080 
1081  loc1 = reg1 + reg13;
1082  reg13 = reg1 - reg13;
1083  loc0 = reg0 + loc1;
1084  loc1 = reg0 - loc1;
1085  tmp6 = loc0;
1086  tmp7 = loc1;
1087  reg0 = loc2;
1088 
1089  VP9_DOTP_CONST_PAIR(reg7, reg9, cospi_24_64, cospi_8_64, reg7, reg9);
1090  VP9_DOTP_CONST_PAIR((-reg5), (-reg11), cospi_8_64, cospi_24_64, reg5,
1091  reg11);
1092 
1093  loc0 = reg9 + reg5;
1094  reg5 = reg9 - reg5;
1095  reg2 = reg6 + loc0;
1096  reg1 = reg6 - loc0;
1097 
1098  loc0 = reg7 + reg11;
1099  reg11 = reg7 - reg11;
1100  loc1 = reg4 + loc0;
1101  loc2 = reg4 - loc0;
1102 
1103  tmp5 = loc1;
1104 
1105  VP9_DOTP_CONST_PAIR(reg5, reg11, cospi_16_64, cospi_16_64, reg5, reg11);
1106  BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1);
1107 
1108  reg10 = loc0;
1109  reg11 = loc1;
1110 
1111  VP9_DOTP_CONST_PAIR(reg3, reg13, cospi_16_64, cospi_16_64, reg3, reg13);
1112  BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5);
1113  reg13 = loc2;
1114 
1115  /* Transpose and store the output */
1116  reg12 = tmp5;
1117  reg14 = tmp6;
1118  reg3 = tmp7;
1119 
1120  /* transpose block */
1121  TRANSPOSE8x8_SH_SH(reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14,
1122  reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14);
1123  ST_SH4(reg0, reg2, reg4, reg6, output, 16);
1124  ST_SH4(reg8, reg10, reg12, reg14, (output + 4 * 16), 16);
1125 
1126  /* transpose block */
1127  TRANSPOSE8x8_SH_SH(reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15,
1128  reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15);
1129  ST_SH4(reg3, reg13, reg11, reg5, (output + 8), 16);
1130  ST_SH4(reg7, reg9, reg1, reg15, (output + 8 + 4 * 16), 16);
1131 }
1132 
1133 static void vp9_idct16x16_1_add_msa(int16_t *input, uint8_t *dst,
1134  int32_t dst_stride)
1135 {
1136  uint8_t i;
1137  int16_t out;
1138  v8i16 vec, res0, res1, res2, res3, res4, res5, res6, res7;
1139  v16u8 dst0, dst1, dst2, dst3, tmp0, tmp1, tmp2, tmp3;
1140 
1141  out = ROUND_POWER_OF_TWO((input[0] * cospi_16_64), VP9_DCT_CONST_BITS);
1142  out = ROUND_POWER_OF_TWO((out * cospi_16_64), VP9_DCT_CONST_BITS);
1143  out = ROUND_POWER_OF_TWO(out, 6);
1144 
1145  vec = __msa_fill_h(out);
1146 
1147  for (i = 4; i--;)
1148  {
1149  LD_UB4(dst, dst_stride, dst0, dst1, dst2, dst3);
1150  UNPCK_UB_SH(dst0, res0, res4);
1151  UNPCK_UB_SH(dst1, res1, res5);
1152  UNPCK_UB_SH(dst2, res2, res6);
1153  UNPCK_UB_SH(dst3, res3, res7);
1154  ADD4(res0, vec, res1, vec, res2, vec, res3, vec, res0, res1, res2,
1155  res3);
1156  ADD4(res4, vec, res5, vec, res6, vec, res7, vec, res4, res5, res6,
1157  res7);
1158  CLIP_SH4_0_255(res0, res1, res2, res3);
1159  CLIP_SH4_0_255(res4, res5, res6, res7);
1160  PCKEV_B4_UB(res4, res0, res5, res1, res6, res2, res7, res3,
1161  tmp0, tmp1, tmp2, tmp3);
1162  ST_UB4(tmp0, tmp1, tmp2, tmp3, dst, dst_stride);
1163  dst += (4 * dst_stride);
1164  }
1165 }
1166 
1167 static void vp9_idct16x16_10_colcol_addblk_msa(int16_t *input, uint8_t *dst,
1168  int32_t dst_stride)
1169 {
1170  int32_t i;
1171  int16_t out_arr[16 * 16] ALLOC_ALIGNED(ALIGNMENT);
1172  int16_t *out = out_arr;
1173 
1174  /* transform rows */
1175  vp9_idct16_1d_columns_msa(input, out);
1176 
1177  /* short case just considers top 4 rows as valid output */
1178  out += 4 * 16;
1179  for (i = 12; i--;) {
1180  __asm__ volatile (
1181  "sw $zero, 0(%[out]) \n\t"
1182  "sw $zero, 4(%[out]) \n\t"
1183  "sw $zero, 8(%[out]) \n\t"
1184  "sw $zero, 12(%[out]) \n\t"
1185  "sw $zero, 16(%[out]) \n\t"
1186  "sw $zero, 20(%[out]) \n\t"
1187  "sw $zero, 24(%[out]) \n\t"
1188  "sw $zero, 28(%[out]) \n\t"
1189 
1190  :
1191  : [out] "r" (out)
1192  );
1193 
1194  out += 16;
1195  }
1196 
1197  out = out_arr;
1198 
1199  /* transform columns */
1200  for (i = 0; i < 2; i++) {
1201  /* process 8 * 16 block */
1202  vp9_idct16_1d_columns_addblk_msa((out + (i << 3)), (dst + (i << 3)),
1203  dst_stride);
1204  }
1205 }
1206 
1207 static void vp9_idct16x16_colcol_addblk_msa(int16_t *input, uint8_t *dst,
1208  int32_t dst_stride)
1209 {
1210  int32_t i;
1211  int16_t out_arr[16 * 16] ALLOC_ALIGNED(ALIGNMENT);
1212  int16_t *out = out_arr;
1213 
1214  /* transform rows */
1215  for (i = 0; i < 2; i++) {
1216  /* process 8 * 16 block */
1217  vp9_idct16_1d_columns_msa((input + (i << 3)), (out + (i << 7)));
1218  }
1219 
1220  /* transform columns */
1221  for (i = 0; i < 2; i++) {
1222  /* process 8 * 16 block */
1223  vp9_idct16_1d_columns_addblk_msa((out + (i << 3)), (dst + (i << 3)),
1224  dst_stride);
1225  }
1226 }
1227 
1228 static void vp9_iadst16_1d_columns_msa(int16_t *input, int16_t *output)
1229 {
1230  v8i16 r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;
1231  v8i16 l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15;
1232 
1233  /* load input data */
1234  LD_SH16(input, 16,
1235  l0, l1, l2, l3, l4, l5, l6, l7,
1236  l8, l9, l10, l11, l12, l13, l14, l15);
1237 
1238  /* ADST in horizontal */
1239  VP9_IADST8x16_1D(l0, l1, l2, l3, l4, l5, l6, l7,
1240  l8, l9, l10, l11, l12, l13, l14, l15,
1241  r0, r1, r2, r3, r4, r5, r6, r7,
1242  r8, r9, r10, r11, r12, r13, r14, r15);
1243 
1244  l1 = -r8;
1245  l3 = -r4;
1246  l13 = -r13;
1247  l15 = -r1;
1248 
1249  TRANSPOSE8x8_SH_SH(r0, l1, r12, l3, r6, r14, r10, r2,
1250  l0, l1, l2, l3, l4, l5, l6, l7);
1251  ST_SH8(l0, l1, l2, l3, l4, l5, l6, l7, output, 16);
1252  TRANSPOSE8x8_SH_SH(r3, r11, r15, r7, r5, l13, r9, l15,
1253  l8, l9, l10, l11, l12, l13, l14, l15);
1254  ST_SH8(l8, l9, l10, l11, l12, l13, l14, l15, (output + 8), 16);
1255 }
1256 
1257 static void vp9_iadst16_1d_columns_addblk_msa(int16_t *input, uint8_t *dst,
1258  int32_t dst_stride)
1259 {
1260  v8i16 v0, v2, v4, v6, k0, k1, k2, k3;
1261  v8i16 r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;
1262  v8i16 out0, out1, out2, out3, out4, out5, out6, out7;
1263  v8i16 out8, out9, out10, out11, out12, out13, out14, out15;
1264  v8i16 g0, g1, g2, g3, g4, g5, g6, g7, g8, g9, g10, g11, g12, g13, g14, g15;
1265  v8i16 h0, h1, h2, h3, h4, h5, h6, h7, h8, h9, h10, h11;
1266  v8i16 res0, res1, res2, res3, res4, res5, res6, res7;
1267  v8i16 res8, res9, res10, res11, res12, res13, res14, res15;
1268  v16u8 dst0, dst1, dst2, dst3, dst4, dst5, dst6, dst7;
1269  v16u8 dst8, dst9, dst10, dst11, dst12, dst13, dst14, dst15;
1270  v16i8 zero = { 0 };
1271 
1272  r0 = LD_SH(input + 0 * 16);
1273  r3 = LD_SH(input + 3 * 16);
1274  r4 = LD_SH(input + 4 * 16);
1275  r7 = LD_SH(input + 7 * 16);
1276  r8 = LD_SH(input + 8 * 16);
1277  r11 = LD_SH(input + 11 * 16);
1278  r12 = LD_SH(input + 12 * 16);
1279  r15 = LD_SH(input + 15 * 16);
1280 
1281  /* stage 1 */
1282  k0 = VP9_SET_COSPI_PAIR(cospi_1_64, cospi_31_64);
1283  k1 = VP9_SET_COSPI_PAIR(cospi_31_64, -cospi_1_64);
1284  k2 = VP9_SET_COSPI_PAIR(cospi_17_64, cospi_15_64);
1285  k3 = VP9_SET_COSPI_PAIR(cospi_15_64, -cospi_17_64);
1286  VP9_MADD_BF(r15, r0, r7, r8, k0, k1, k2, k3, g0, g1, g2, g3);
1287  k0 = VP9_SET_COSPI_PAIR(cospi_9_64, cospi_23_64);
1288  k1 = VP9_SET_COSPI_PAIR(cospi_23_64, -cospi_9_64);
1289  k2 = VP9_SET_COSPI_PAIR(cospi_25_64, cospi_7_64);
1290  k3 = VP9_SET_COSPI_PAIR(cospi_7_64, -cospi_25_64);
1291  VP9_MADD_BF(r11, r4, r3, r12, k0, k1, k2, k3, g8, g9, g10, g11);
1292  BUTTERFLY_4(g0, g2, g10, g8, h8, h9, v2, v0);
1293  k0 = VP9_SET_COSPI_PAIR(cospi_4_64, cospi_28_64);
1294  k1 = VP9_SET_COSPI_PAIR(cospi_28_64, -cospi_4_64);
1295  k2 = VP9_SET_COSPI_PAIR(-cospi_28_64, cospi_4_64);
1296  VP9_MADD_BF(g1, g3, g9, g11, k0, k1, k2, k0, h0, h1, h2, h3);
1297 
1298  r1 = LD_SH(input + 1 * 16);
1299  r2 = LD_SH(input + 2 * 16);
1300  r5 = LD_SH(input + 5 * 16);
1301  r6 = LD_SH(input + 6 * 16);
1302  r9 = LD_SH(input + 9 * 16);
1303  r10 = LD_SH(input + 10 * 16);
1304  r13 = LD_SH(input + 13 * 16);
1305  r14 = LD_SH(input + 14 * 16);
1306 
1307  k0 = VP9_SET_COSPI_PAIR(cospi_5_64, cospi_27_64);
1308  k1 = VP9_SET_COSPI_PAIR(cospi_27_64, -cospi_5_64);
1309  k2 = VP9_SET_COSPI_PAIR(cospi_21_64, cospi_11_64);
1310  k3 = VP9_SET_COSPI_PAIR(cospi_11_64, -cospi_21_64);
1311  VP9_MADD_BF(r13, r2, r5, r10, k0, k1, k2, k3, g4, g5, g6, g7);
1312  k0 = VP9_SET_COSPI_PAIR(cospi_13_64, cospi_19_64);
1313  k1 = VP9_SET_COSPI_PAIR(cospi_19_64, -cospi_13_64);
1314  k2 = VP9_SET_COSPI_PAIR(cospi_29_64, cospi_3_64);
1315  k3 = VP9_SET_COSPI_PAIR(cospi_3_64, -cospi_29_64);
1316  VP9_MADD_BF(r9, r6, r1, r14, k0, k1, k2, k3, g12, g13, g14, g15);
1317  BUTTERFLY_4(g4, g6, g14, g12, h10, h11, v6, v4);
1318  BUTTERFLY_4(h8, h9, h11, h10, out0, out1, h11, h10);
1319  out1 = -out1;
1320  SRARI_H2_SH(out0, out1, 6);
1321  dst0 = LD_UB(dst + 0 * dst_stride);
1322  dst1 = LD_UB(dst + 15 * dst_stride);
1323  ILVR_B2_SH(zero, dst0, zero, dst1, res0, res1);
1324  ADD2(res0, out0, res1, out1, res0, res1);
1325  CLIP_SH2_0_255(res0, res1);
1326  PCKEV_B2_SH(res0, res0, res1, res1, res0, res1);
1327  ST8x1_UB(res0, dst);
1328  ST8x1_UB(res1, dst + 15 * dst_stride);
1329 
1330  k0 = VP9_SET_COSPI_PAIR(cospi_12_64, cospi_20_64);
1331  k1 = VP9_SET_COSPI_PAIR(-cospi_20_64, cospi_12_64);
1332  k2 = VP9_SET_COSPI_PAIR(cospi_20_64, -cospi_12_64);
1333  VP9_MADD_BF(g7, g5, g15, g13, k0, k1, k2, k0, h4, h5, h6, h7);
1334  BUTTERFLY_4(h0, h2, h6, h4, out8, out9, out11, out10);
1335  out8 = -out8;
1336 
1337  SRARI_H2_SH(out8, out9, 6);
1338  dst8 = LD_UB(dst + 1 * dst_stride);
1339  dst9 = LD_UB(dst + 14 * dst_stride);
1340  ILVR_B2_SH(zero, dst8, zero, dst9, res8, res9);
1341  ADD2(res8, out8, res9, out9, res8, res9);
1342  CLIP_SH2_0_255(res8, res9);
1343  PCKEV_B2_SH(res8, res8, res9, res9, res8, res9);
1344  ST8x1_UB(res8, dst + dst_stride);
1345  ST8x1_UB(res9, dst + 14 * dst_stride);
1346 
1347  k0 = VP9_SET_COSPI_PAIR(cospi_8_64, cospi_24_64);
1348  k1 = VP9_SET_COSPI_PAIR(cospi_24_64, -cospi_8_64);
1349  k2 = VP9_SET_COSPI_PAIR(-cospi_24_64, cospi_8_64);
1350  VP9_MADD_BF(v0, v2, v4, v6, k0, k1, k2, k0, out4, out6, out5, out7);
1351  out4 = -out4;
1352  SRARI_H2_SH(out4, out5, 6);
1353  dst4 = LD_UB(dst + 3 * dst_stride);
1354  dst5 = LD_UB(dst + 12 * dst_stride);
1355  ILVR_B2_SH(zero, dst4, zero, dst5, res4, res5);
1356  ADD2(res4, out4, res5, out5, res4, res5);
1357  CLIP_SH2_0_255(res4, res5);
1358  PCKEV_B2_SH(res4, res4, res5, res5, res4, res5);
1359  ST8x1_UB(res4, dst + 3 * dst_stride);
1360  ST8x1_UB(res5, dst + 12 * dst_stride);
1361 
1362  VP9_MADD_BF(h1, h3, h5, h7, k0, k1, k2, k0, out12, out14, out13, out15);
1363  out13 = -out13;
1364  SRARI_H2_SH(out12, out13, 6);
1365  dst12 = LD_UB(dst + 2 * dst_stride);
1366  dst13 = LD_UB(dst + 13 * dst_stride);
1367  ILVR_B2_SH(zero, dst12, zero, dst13, res12, res13);
1368  ADD2(res12, out12, res13, out13, res12, res13);
1369  CLIP_SH2_0_255(res12, res13);
1370  PCKEV_B2_SH(res12, res12, res13, res13, res12, res13);
1371  ST8x1_UB(res12, dst + 2 * dst_stride);
1372  ST8x1_UB(res13, dst + 13 * dst_stride);
1373 
1374  k0 = VP9_SET_COSPI_PAIR(cospi_16_64, cospi_16_64);
1375  k3 = VP9_SET_COSPI_PAIR(-cospi_16_64, cospi_16_64);
1376  VP9_MADD_SHORT(out6, out7, k0, k3, out6, out7);
1377  SRARI_H2_SH(out6, out7, 6);
1378  dst6 = LD_UB(dst + 4 * dst_stride);
1379  dst7 = LD_UB(dst + 11 * dst_stride);
1380  ILVR_B2_SH(zero, dst6, zero, dst7, res6, res7);
1381  ADD2(res6, out6, res7, out7, res6, res7);
1382  CLIP_SH2_0_255(res6, res7);
1383  PCKEV_B2_SH(res6, res6, res7, res7, res6, res7);
1384  ST8x1_UB(res6, dst + 4 * dst_stride);
1385  ST8x1_UB(res7, dst + 11 * dst_stride);
1386 
1387  VP9_MADD_SHORT(out10, out11, k0, k3, out10, out11);
1388  SRARI_H2_SH(out10, out11, 6);
1389  dst10 = LD_UB(dst + 6 * dst_stride);
1390  dst11 = LD_UB(dst + 9 * dst_stride);
1391  ILVR_B2_SH(zero, dst10, zero, dst11, res10, res11);
1392  ADD2(res10, out10, res11, out11, res10, res11);
1393  CLIP_SH2_0_255(res10, res11);
1394  PCKEV_B2_SH(res10, res10, res11, res11, res10, res11);
1395  ST8x1_UB(res10, dst + 6 * dst_stride);
1396  ST8x1_UB(res11, dst + 9 * dst_stride);
1397 
1398  k1 = VP9_SET_COSPI_PAIR(-cospi_16_64, -cospi_16_64);
1399  k2 = VP9_SET_COSPI_PAIR(cospi_16_64, -cospi_16_64);
1400  VP9_MADD_SHORT(h10, h11, k1, k2, out2, out3);
1401  SRARI_H2_SH(out2, out3, 6);
1402  dst2 = LD_UB(dst + 7 * dst_stride);
1403  dst3 = LD_UB(dst + 8 * dst_stride);
1404  ILVR_B2_SH(zero, dst2, zero, dst3, res2, res3);
1405  ADD2(res2, out2, res3, out3, res2, res3);
1406  CLIP_SH2_0_255(res2, res3);
1407  PCKEV_B2_SH(res2, res2, res3, res3, res2, res3);
1408  ST8x1_UB(res2, dst + 7 * dst_stride);
1409  ST8x1_UB(res3, dst + 8 * dst_stride);
1410 
1411  VP9_MADD_SHORT(out14, out15, k1, k2, out14, out15);
1412  SRARI_H2_SH(out14, out15, 6);
1413  dst14 = LD_UB(dst + 5 * dst_stride);
1414  dst15 = LD_UB(dst + 10 * dst_stride);
1415  ILVR_B2_SH(zero, dst14, zero, dst15, res14, res15);
1416  ADD2(res14, out14, res15, out15, res14, res15);
1417  CLIP_SH2_0_255(res14, res15);
1418  PCKEV_B2_SH(res14, res14, res15, res15, res14, res15);
1419  ST8x1_UB(res14, dst + 5 * dst_stride);
1420  ST8x1_UB(res15, dst + 10 * dst_stride);
1421 }
1422 
1423 static void vp9_iadst16x16_colcol_addblk_msa(int16_t *input, uint8_t *dst,
1424  int32_t dst_stride)
1425 {
1426  int16_t out_arr[16 * 16] ALLOC_ALIGNED(ALIGNMENT);
1427  int16_t *out = out_arr;
1428  int32_t i;
1429 
1430  /* transform rows */
1431  for (i = 0; i < 2; i++) {
1432  /* process 16 * 8 block */
1433  vp9_iadst16_1d_columns_msa((input + (i << 3)), (out + (i << 7)));
1434  }
1435 
1436  /* transform columns */
1437  for (i = 0; i < 2; i++) {
1438  /* process 8 * 16 block */
1439  vp9_iadst16_1d_columns_addblk_msa((out + (i << 3)), (dst + (i << 3)),
1440  dst_stride);
1441  }
1442 }
1443 
1444 static void vp9_iadst_idct_16x16_add_msa(int16_t *input, uint8_t *dst,
1445  int32_t dst_stride, int32_t eob)
1446 {
1447  int32_t i;
1448  int16_t out[16 * 16];
1449  int16_t *out_ptr = &out[0];
1450 
1451  /* transform rows */
1452  for (i = 0; i < 2; i++) {
1453  /* process 8 * 16 block */
1454  vp9_iadst16_1d_columns_msa((input + (i << 3)), (out_ptr + (i << 7)));
1455  }
1456 
1457  /* transform columns */
1458  for (i = 0; i < 2; i++) {
1459  /* process 8 * 16 block */
1460  vp9_idct16_1d_columns_addblk_msa((out_ptr + (i << 3)),
1461  (dst + (i << 3)), dst_stride);
1462  }
1463 }
1464 
1465 static void vp9_idct_iadst_16x16_add_msa(int16_t *input, uint8_t *dst,
1466  int32_t dst_stride, int32_t eob)
1467 {
1468  int32_t i;
1469  int16_t out[16 * 16];
1470  int16_t *out_ptr = &out[0];
1471 
1472  /* transform rows */
1473  for (i = 0; i < 2; i++) {
1474  /* process 8 * 16 block */
1475  vp9_idct16_1d_columns_msa((input + (i << 3)), (out_ptr + (i << 7)));
1476  }
1477 
1478  /* transform columns */
1479  for (i = 0; i < 2; i++) {
1480  /* process 8 * 16 block */
1481  vp9_iadst16_1d_columns_addblk_msa((out_ptr + (i << 3)),
1482  (dst + (i << 3)), dst_stride);
1483  }
1484 }
1485 
1486 static void vp9_idct_butterfly_transpose_store(int16_t *tmp_buf,
1487  int16_t *tmp_eve_buf,
1488  int16_t *tmp_odd_buf,
1489  int16_t *dst)
1490 {
1491  v8i16 vec0, vec1, vec2, vec3, loc0, loc1, loc2, loc3;
1492  v8i16 m0, m1, m2, m3, m4, m5, m6, m7, n0, n1, n2, n3, n4, n5, n6, n7;
1493 
1494  /* FINAL BUTTERFLY : Dependency on Even & Odd */
1495  vec0 = LD_SH(tmp_odd_buf);
1496  vec1 = LD_SH(tmp_odd_buf + 9 * 8);
1497  vec2 = LD_SH(tmp_odd_buf + 14 * 8);
1498  vec3 = LD_SH(tmp_odd_buf + 6 * 8);
1499  loc0 = LD_SH(tmp_eve_buf);
1500  loc1 = LD_SH(tmp_eve_buf + 8 * 8);
1501  loc2 = LD_SH(tmp_eve_buf + 4 * 8);
1502  loc3 = LD_SH(tmp_eve_buf + 12 * 8);
1503 
1504  ADD4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, m0, m4, m2, m6);
1505 
1506  ST_SH((loc0 - vec3), (tmp_buf + 31 * 8));
1507  ST_SH((loc1 - vec2), (tmp_buf + 23 * 8));
1508  ST_SH((loc2 - vec1), (tmp_buf + 27 * 8));
1509  ST_SH((loc3 - vec0), (tmp_buf + 19 * 8));
1510 
1511  /* Load 8 & Store 8 */
1512  vec0 = LD_SH(tmp_odd_buf + 4 * 8);
1513  vec1 = LD_SH(tmp_odd_buf + 13 * 8);
1514  vec2 = LD_SH(tmp_odd_buf + 10 * 8);
1515  vec3 = LD_SH(tmp_odd_buf + 3 * 8);
1516  loc0 = LD_SH(tmp_eve_buf + 2 * 8);
1517  loc1 = LD_SH(tmp_eve_buf + 10 * 8);
1518  loc2 = LD_SH(tmp_eve_buf + 6 * 8);
1519  loc3 = LD_SH(tmp_eve_buf + 14 * 8);
1520 
1521  ADD4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, m1, m5, m3, m7);
1522 
1523  ST_SH((loc0 - vec3), (tmp_buf + 29 * 8));
1524  ST_SH((loc1 - vec2), (tmp_buf + 21 * 8));
1525  ST_SH((loc2 - vec1), (tmp_buf + 25 * 8));
1526  ST_SH((loc3 - vec0), (tmp_buf + 17 * 8));
1527 
1528  /* Load 8 & Store 8 */
1529  vec0 = LD_SH(tmp_odd_buf + 2 * 8);
1530  vec1 = LD_SH(tmp_odd_buf + 11 * 8);
1531  vec2 = LD_SH(tmp_odd_buf + 12 * 8);
1532  vec3 = LD_SH(tmp_odd_buf + 7 * 8);
1533  loc0 = LD_SH(tmp_eve_buf + 1 * 8);
1534  loc1 = LD_SH(tmp_eve_buf + 9 * 8);
1535  loc2 = LD_SH(tmp_eve_buf + 5 * 8);
1536  loc3 = LD_SH(tmp_eve_buf + 13 * 8);
1537 
1538  ADD4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, n0, n4, n2, n6);
1539 
1540  ST_SH((loc0 - vec3), (tmp_buf + 30 * 8));
1541  ST_SH((loc1 - vec2), (tmp_buf + 22 * 8));
1542  ST_SH((loc2 - vec1), (tmp_buf + 26 * 8));
1543  ST_SH((loc3 - vec0), (tmp_buf + 18 * 8));
1544 
1545  /* Load 8 & Store 8 */
1546  vec0 = LD_SH(tmp_odd_buf + 5 * 8);
1547  vec1 = LD_SH(tmp_odd_buf + 15 * 8);
1548  vec2 = LD_SH(tmp_odd_buf + 8 * 8);
1549  vec3 = LD_SH(tmp_odd_buf + 1 * 8);
1550  loc0 = LD_SH(tmp_eve_buf + 3 * 8);
1551  loc1 = LD_SH(tmp_eve_buf + 11 * 8);
1552  loc2 = LD_SH(tmp_eve_buf + 7 * 8);
1553  loc3 = LD_SH(tmp_eve_buf + 15 * 8);
1554 
1555  ADD4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, n1, n5, n3, n7);
1556 
1557  ST_SH((loc0 - vec3), (tmp_buf + 28 * 8));
1558  ST_SH((loc1 - vec2), (tmp_buf + 20 * 8));
1559  ST_SH((loc2 - vec1), (tmp_buf + 24 * 8));
1560  ST_SH((loc3 - vec0), (tmp_buf + 16 * 8));
1561 
1562  /* Transpose : 16 vectors */
1563  /* 1st & 2nd 8x8 */
1564  TRANSPOSE8x8_SH_SH(m0, n0, m1, n1, m2, n2, m3, n3,
1565  m0, n0, m1, n1, m2, n2, m3, n3);
1566  ST_SH4(m0, n0, m1, n1, (dst + 0), 32);
1567  ST_SH4(m2, n2, m3, n3, (dst + 4 * 32), 32);
1568 
1569  TRANSPOSE8x8_SH_SH(m4, n4, m5, n5, m6, n6, m7, n7,
1570  m4, n4, m5, n5, m6, n6, m7, n7);
1571  ST_SH4(m4, n4, m5, n5, (dst + 8), 32);
1572  ST_SH4(m6, n6, m7, n7, (dst + 8 + 4 * 32), 32);
1573 
1574  /* 3rd & 4th 8x8 */
1575  LD_SH8((tmp_buf + 8 * 16), 8, m0, n0, m1, n1, m2, n2, m3, n3);
1576  LD_SH8((tmp_buf + 12 * 16), 8, m4, n4, m5, n5, m6, n6, m7, n7);
1577  TRANSPOSE8x8_SH_SH(m0, n0, m1, n1, m2, n2, m3, n3,
1578  m0, n0, m1, n1, m2, n2, m3, n3);
1579  ST_SH4(m0, n0, m1, n1, (dst + 16), 32);
1580  ST_SH4(m2, n2, m3, n3, (dst + 16 + 4 * 32), 32);
1581 
1582  TRANSPOSE8x8_SH_SH(m4, n4, m5, n5, m6, n6, m7, n7,
1583  m4, n4, m5, n5, m6, n6, m7, n7);
1584  ST_SH4(m4, n4, m5, n5, (dst + 24), 32);
1585  ST_SH4(m6, n6, m7, n7, (dst + 24 + 4 * 32), 32);
1586 }
1587 
1588 static void vp9_idct8x32_column_even_process_store(int16_t *tmp_buf,
1589  int16_t *tmp_eve_buf)
1590 {
1591  v8i16 vec0, vec1, vec2, vec3, loc0, loc1, loc2, loc3;
1592  v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
1593  v8i16 stp0, stp1, stp2, stp3, stp4, stp5, stp6, stp7;
1594 
1595  /* Even stage 1 */
1596  LD_SH8(tmp_buf, (4 * 32), reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
1597  tmp_buf += (2 * 32);
1598 
1599  VP9_DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7);
1600  VP9_DOTP_CONST_PAIR(reg5, reg3, cospi_12_64, cospi_20_64, reg5, reg3);
1601  BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0);
1602  VP9_DOTP_CONST_PAIR(vec2, vec0, cospi_16_64, cospi_16_64, loc2, loc3);
1603 
1604  loc1 = vec3;
1605  loc0 = vec1;
1606 
1607  VP9_DOTP_CONST_PAIR(reg0, reg4, cospi_16_64, cospi_16_64, reg0, reg4);
1608  VP9_DOTP_CONST_PAIR(reg2, reg6, cospi_24_64, cospi_8_64, reg2, reg6);
1609  BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0);
1610  BUTTERFLY_4(vec0, vec1, loc1, loc0, stp3, stp0, stp7, stp4);
1611  BUTTERFLY_4(vec2, vec3, loc3, loc2, stp2, stp1, stp6, stp5);
1612 
1613  /* Even stage 2 */
1614  /* Load 8 */
1615  LD_SH8(tmp_buf, (4 * 32), reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
1616 
1617  VP9_DOTP_CONST_PAIR(reg0, reg7, cospi_30_64, cospi_2_64, reg0, reg7);
1618  VP9_DOTP_CONST_PAIR(reg4, reg3, cospi_14_64, cospi_18_64, reg4, reg3);
1619  VP9_DOTP_CONST_PAIR(reg2, reg5, cospi_22_64, cospi_10_64, reg2, reg5);
1620  VP9_DOTP_CONST_PAIR(reg6, reg1, cospi_6_64, cospi_26_64, reg6, reg1);
1621 
1622  vec0 = reg0 + reg4;
1623  reg0 = reg0 - reg4;
1624  reg4 = reg6 + reg2;
1625  reg6 = reg6 - reg2;
1626  reg2 = reg1 + reg5;
1627  reg1 = reg1 - reg5;
1628  reg5 = reg7 + reg3;
1629  reg7 = reg7 - reg3;
1630  reg3 = vec0;
1631 
1632  vec1 = reg2;
1633  reg2 = reg3 + reg4;
1634  reg3 = reg3 - reg4;
1635  reg4 = reg5 - vec1;
1636  reg5 = reg5 + vec1;
1637 
1638  VP9_DOTP_CONST_PAIR(reg7, reg0, cospi_24_64, cospi_8_64, reg0, reg7);
1639  VP9_DOTP_CONST_PAIR((-reg6), reg1, cospi_24_64, cospi_8_64, reg6, reg1);
1640 
1641  vec0 = reg0 - reg6;
1642  reg0 = reg0 + reg6;
1643  vec1 = reg7 - reg1;
1644  reg7 = reg7 + reg1;
1645 
1646  VP9_DOTP_CONST_PAIR(vec1, vec0, cospi_16_64, cospi_16_64, reg6, reg1);
1647  VP9_DOTP_CONST_PAIR(reg4, reg3, cospi_16_64, cospi_16_64, reg3, reg4);
1648 
1649  /* Even stage 3 : Dependency on Even stage 1 & Even stage 2 */
1650  /* Store 8 */
1651  BUTTERFLY_4(stp0, stp1, reg7, reg5, loc1, loc3, loc2, loc0);
1652  ST_SH2(loc1, loc3, tmp_eve_buf, 8);
1653  ST_SH2(loc2, loc0, (tmp_eve_buf + 14 * 8), 8);
1654 
1655  BUTTERFLY_4(stp2, stp3, reg4, reg1, loc1, loc3, loc2, loc0);
1656  ST_SH2(loc1, loc3, (tmp_eve_buf + 2 * 8), 8);
1657  ST_SH2(loc2, loc0, (tmp_eve_buf + 12 * 8), 8);
1658 
1659  /* Store 8 */
1660  BUTTERFLY_4(stp4, stp5, reg6, reg3, loc1, loc3, loc2, loc0);
1661  ST_SH2(loc1, loc3, (tmp_eve_buf + 4 * 8), 8);
1662  ST_SH2(loc2, loc0, (tmp_eve_buf + 10 * 8), 8);
1663 
1664  BUTTERFLY_4(stp6, stp7, reg2, reg0, loc1, loc3, loc2, loc0);
1665  ST_SH2(loc1, loc3, (tmp_eve_buf + 6 * 8), 8);
1666  ST_SH2(loc2, loc0, (tmp_eve_buf + 8 * 8), 8);
1667 }
1668 
1669 static void vp9_idct8x32_column_odd_process_store(int16_t *tmp_buf,
1670  int16_t *tmp_odd_buf)
1671 {
1672  v8i16 vec0, vec1, vec2, vec3, loc0, loc1, loc2, loc3;
1673  v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
1674 
1675  /* Odd stage 1 */
1676  reg0 = LD_SH(tmp_buf + 32);
1677  reg1 = LD_SH(tmp_buf + 7 * 32);
1678  reg2 = LD_SH(tmp_buf + 9 * 32);
1679  reg3 = LD_SH(tmp_buf + 15 * 32);
1680  reg4 = LD_SH(tmp_buf + 17 * 32);
1681  reg5 = LD_SH(tmp_buf + 23 * 32);
1682  reg6 = LD_SH(tmp_buf + 25 * 32);
1683  reg7 = LD_SH(tmp_buf + 31 * 32);
1684 
1685  VP9_DOTP_CONST_PAIR(reg0, reg7, cospi_31_64, cospi_1_64, reg0, reg7);
1686  VP9_DOTP_CONST_PAIR(reg4, reg3, cospi_15_64, cospi_17_64, reg3, reg4);
1687  VP9_DOTP_CONST_PAIR(reg2, reg5, cospi_23_64, cospi_9_64, reg2, reg5);
1688  VP9_DOTP_CONST_PAIR(reg6, reg1, cospi_7_64, cospi_25_64, reg1, reg6);
1689 
1690  vec0 = reg0 + reg3;
1691  reg0 = reg0 - reg3;
1692  reg3 = reg7 + reg4;
1693  reg7 = reg7 - reg4;
1694  reg4 = reg1 + reg2;
1695  reg1 = reg1 - reg2;
1696  reg2 = reg6 + reg5;
1697  reg6 = reg6 - reg5;
1698  reg5 = vec0;
1699 
1700  /* 4 Stores */
1701  ADD2(reg5, reg4, reg3, reg2, vec0, vec1);
1702  ST_SH2(vec0, vec1, (tmp_odd_buf + 4 * 8), 8);
1703  SUB2(reg5, reg4, reg3, reg2, vec0, vec1);
1704  VP9_DOTP_CONST_PAIR(vec1, vec0, cospi_24_64, cospi_8_64, vec0, vec1);
1705  ST_SH2(vec0, vec1, tmp_odd_buf, 8);
1706 
1707  /* 4 Stores */
1708  VP9_DOTP_CONST_PAIR(reg7, reg0, cospi_28_64, cospi_4_64, reg0, reg7);
1709  VP9_DOTP_CONST_PAIR(reg6, reg1, -cospi_4_64, cospi_28_64, reg1, reg6);
1710  BUTTERFLY_4(reg0, reg7, reg6, reg1, vec0, vec1, vec2, vec3);
1711  ST_SH2(vec0, vec1, (tmp_odd_buf + 6 * 8), 8);
1712  VP9_DOTP_CONST_PAIR(vec2, vec3, cospi_24_64, cospi_8_64, vec2, vec3);
1713  ST_SH2(vec2, vec3, (tmp_odd_buf + 2 * 8), 8);
1714 
1715  /* Odd stage 2 */
1716  /* 8 loads */
1717  reg0 = LD_SH(tmp_buf + 3 * 32);
1718  reg1 = LD_SH(tmp_buf + 5 * 32);
1719  reg2 = LD_SH(tmp_buf + 11 * 32);
1720  reg3 = LD_SH(tmp_buf + 13 * 32);
1721  reg4 = LD_SH(tmp_buf + 19 * 32);
1722  reg5 = LD_SH(tmp_buf + 21 * 32);
1723  reg6 = LD_SH(tmp_buf + 27 * 32);
1724  reg7 = LD_SH(tmp_buf + 29 * 32);
1725 
1726  VP9_DOTP_CONST_PAIR(reg1, reg6, cospi_27_64, cospi_5_64, reg1, reg6);
1727  VP9_DOTP_CONST_PAIR(reg5, reg2, cospi_11_64, cospi_21_64, reg2, reg5);
1728  VP9_DOTP_CONST_PAIR(reg3, reg4, cospi_19_64, cospi_13_64, reg3, reg4);
1729  VP9_DOTP_CONST_PAIR(reg7, reg0, cospi_3_64, cospi_29_64, reg0, reg7);
1730 
1731  /* 4 Stores */
1732  SUB4(reg1, reg2, reg6, reg5, reg0, reg3, reg7, reg4,
1733  vec0, vec1, vec2, vec3);
1734  VP9_DOTP_CONST_PAIR(vec1, vec0, cospi_12_64, cospi_20_64, loc0, loc1);
1735  VP9_DOTP_CONST_PAIR(vec3, vec2, -cospi_20_64, cospi_12_64, loc2, loc3);
1736  BUTTERFLY_4(loc2, loc3, loc1, loc0, vec0, vec1, vec3, vec2);
1737  ST_SH2(vec0, vec1, (tmp_odd_buf + 12 * 8), 3 * 8);
1738  VP9_DOTP_CONST_PAIR(vec3, vec2, -cospi_8_64, cospi_24_64, vec0, vec1);
1739  ST_SH2(vec0, vec1, (tmp_odd_buf + 10 * 8), 8);
1740 
1741  /* 4 Stores */
1742  ADD4(reg0, reg3, reg1, reg2, reg5, reg6, reg4, reg7,
1743  vec0, vec1, vec2, vec3);
1744  BUTTERFLY_4(vec0, vec3, vec2, vec1, reg0, reg1, reg3, reg2);
1745  ST_SH2(reg0, reg1, (tmp_odd_buf + 13 * 8), 8);
1746  VP9_DOTP_CONST_PAIR(reg3, reg2, -cospi_8_64, cospi_24_64, reg0, reg1);
1747  ST_SH2(reg0, reg1, (tmp_odd_buf + 8 * 8), 8);
1748 
1749  /* Odd stage 3 : Dependency on Odd stage 1 & Odd stage 2 */
1750  /* Load 8 & Store 8 */
1751  LD_SH4(tmp_odd_buf, 8, reg0, reg1, reg2, reg3);
1752  LD_SH4((tmp_odd_buf + 8 * 8), 8, reg4, reg5, reg6, reg7);
1753 
1754  ADD4(reg0, reg4, reg1, reg5, reg2, reg6, reg3, reg7,
1755  loc0, loc1, loc2, loc3);
1756  ST_SH4(loc0, loc1, loc2, loc3, tmp_odd_buf, 8);
1757 
1758  SUB2(reg0, reg4, reg1, reg5, vec0, vec1);
1759  VP9_DOTP_CONST_PAIR(vec1, vec0, cospi_16_64, cospi_16_64, loc0, loc1);
1760 
1761  SUB2(reg2, reg6, reg3, reg7, vec0, vec1);
1762  VP9_DOTP_CONST_PAIR(vec1, vec0, cospi_16_64, cospi_16_64, loc2, loc3);
1763  ST_SH4(loc0, loc1, loc2, loc3, (tmp_odd_buf + 8 * 8), 8);
1764 
1765  /* Load 8 & Store 8 */
1766  LD_SH4((tmp_odd_buf + 4 * 8), 8, reg1, reg2, reg0, reg3);
1767  LD_SH4((tmp_odd_buf + 12 * 8), 8, reg4, reg5, reg6, reg7);
1768 
1769  ADD4(reg0, reg4, reg1, reg5, reg2, reg6, reg3, reg7,
1770  loc0, loc1, loc2, loc3);
1771  ST_SH4(loc0, loc1, loc2, loc3, (tmp_odd_buf + 4 * 8), 8);
1772 
1773  SUB2(reg0, reg4, reg3, reg7, vec0, vec1);
1774  VP9_DOTP_CONST_PAIR(vec1, vec0, cospi_16_64, cospi_16_64, loc0, loc1);
1775 
1776  SUB2(reg1, reg5, reg2, reg6, vec0, vec1);
1777  VP9_DOTP_CONST_PAIR(vec1, vec0, cospi_16_64, cospi_16_64, loc2, loc3);
1778  ST_SH4(loc0, loc1, loc2, loc3, (tmp_odd_buf + 12 * 8), 8);
1779 }
1780 
1781 static void vp9_idct8x32_column_butterfly_addblk(int16_t *tmp_eve_buf,
1782  int16_t *tmp_odd_buf,
1783  uint8_t *dst,
1784  int32_t dst_stride)
1785 {
1786  v8i16 vec0, vec1, vec2, vec3, loc0, loc1, loc2, loc3;
1787  v8i16 m0, m1, m2, m3, m4, m5, m6, m7, n0, n1, n2, n3, n4, n5, n6, n7;
1788 
1789  /* FINAL BUTTERFLY : Dependency on Even & Odd */
1790  vec0 = LD_SH(tmp_odd_buf);
1791  vec1 = LD_SH(tmp_odd_buf + 9 * 8);
1792  vec2 = LD_SH(tmp_odd_buf + 14 * 8);
1793  vec3 = LD_SH(tmp_odd_buf + 6 * 8);
1794  loc0 = LD_SH(tmp_eve_buf);
1795  loc1 = LD_SH(tmp_eve_buf + 8 * 8);
1796  loc2 = LD_SH(tmp_eve_buf + 4 * 8);
1797  loc3 = LD_SH(tmp_eve_buf + 12 * 8);
1798 
1799  ADD4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, m0, m4, m2, m6);
1800  SRARI_H4_SH(m0, m2, m4, m6, 6);
1801  VP9_ADDBLK_ST8x4_UB(dst, (4 * dst_stride), m0, m2, m4, m6);
1802 
1803  SUB4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, m6, m2, m4, m0);
1804  SRARI_H4_SH(m0, m2, m4, m6, 6);
1805  VP9_ADDBLK_ST8x4_UB((dst + 19 * dst_stride), (4 * dst_stride),
1806  m0, m2, m4, m6);
1807 
1808  /* Load 8 & Store 8 */
1809  vec0 = LD_SH(tmp_odd_buf + 4 * 8);
1810  vec1 = LD_SH(tmp_odd_buf + 13 * 8);
1811  vec2 = LD_SH(tmp_odd_buf + 10 * 8);
1812  vec3 = LD_SH(tmp_odd_buf + 3 * 8);
1813  loc0 = LD_SH(tmp_eve_buf + 2 * 8);
1814  loc1 = LD_SH(tmp_eve_buf + 10 * 8);
1815  loc2 = LD_SH(tmp_eve_buf + 6 * 8);
1816  loc3 = LD_SH(tmp_eve_buf + 14 * 8);
1817 
1818  ADD4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, m1, m5, m3, m7);
1819  SRARI_H4_SH(m1, m3, m5, m7, 6);
1820  VP9_ADDBLK_ST8x4_UB((dst + 2 * dst_stride), (4 * dst_stride),
1821  m1, m3, m5, m7);
1822 
1823  SUB4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, m7, m3, m5, m1);
1824  SRARI_H4_SH(m1, m3, m5, m7, 6);
1825  VP9_ADDBLK_ST8x4_UB((dst + 17 * dst_stride), (4 * dst_stride),
1826  m1, m3, m5, m7);
1827 
1828  /* Load 8 & Store 8 */
1829  vec0 = LD_SH(tmp_odd_buf + 2 * 8);
1830  vec1 = LD_SH(tmp_odd_buf + 11 * 8);
1831  vec2 = LD_SH(tmp_odd_buf + 12 * 8);
1832  vec3 = LD_SH(tmp_odd_buf + 7 * 8);
1833  loc0 = LD_SH(tmp_eve_buf + 1 * 8);
1834  loc1 = LD_SH(tmp_eve_buf + 9 * 8);
1835  loc2 = LD_SH(tmp_eve_buf + 5 * 8);
1836  loc3 = LD_SH(tmp_eve_buf + 13 * 8);
1837 
1838  ADD4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, n0, n4, n2, n6);
1839  SRARI_H4_SH(n0, n2, n4, n6, 6);
1840  VP9_ADDBLK_ST8x4_UB((dst + 1 * dst_stride), (4 * dst_stride),
1841  n0, n2, n4, n6);
1842 
1843  SUB4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, n6, n2, n4, n0);
1844  SRARI_H4_SH(n0, n2, n4, n6, 6);
1845  VP9_ADDBLK_ST8x4_UB((dst + 18 * dst_stride), (4 * dst_stride),
1846  n0, n2, n4, n6);
1847 
1848  /* Load 8 & Store 8 */
1849  vec0 = LD_SH(tmp_odd_buf + 5 * 8);
1850  vec1 = LD_SH(tmp_odd_buf + 15 * 8);
1851  vec2 = LD_SH(tmp_odd_buf + 8 * 8);
1852  vec3 = LD_SH(tmp_odd_buf + 1 * 8);
1853  loc0 = LD_SH(tmp_eve_buf + 3 * 8);
1854  loc1 = LD_SH(tmp_eve_buf + 11 * 8);
1855  loc2 = LD_SH(tmp_eve_buf + 7 * 8);
1856  loc3 = LD_SH(tmp_eve_buf + 15 * 8);
1857 
1858  ADD4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, n1, n5, n3, n7);
1859  SRARI_H4_SH(n1, n3, n5, n7, 6);
1860  VP9_ADDBLK_ST8x4_UB((dst + 3 * dst_stride), (4 * dst_stride),
1861  n1, n3, n5, n7);
1862 
1863  SUB4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, n7, n3, n5, n1);
1864  SRARI_H4_SH(n1, n3, n5, n7, 6);
1865  VP9_ADDBLK_ST8x4_UB((dst + 16 * dst_stride), (4 * dst_stride),
1866  n1, n3, n5, n7);
1867 }
1868 
1869 static void vp9_idct8x32_1d_columns_addblk_msa(int16_t *input, uint8_t *dst,
1870  int32_t dst_stride)
1871 {
1872  int16_t tmp_odd_buf[16 * 8] ALLOC_ALIGNED(ALIGNMENT);
1873  int16_t tmp_eve_buf[16 * 8] ALLOC_ALIGNED(ALIGNMENT);
1874 
1875  vp9_idct8x32_column_even_process_store(input, &tmp_eve_buf[0]);
1876  vp9_idct8x32_column_odd_process_store(input, &tmp_odd_buf[0]);
1877  vp9_idct8x32_column_butterfly_addblk(&tmp_eve_buf[0], &tmp_odd_buf[0],
1878  dst, dst_stride);
1879 }
1880 
1881 static void vp9_idct8x32_1d_columns_msa(int16_t *input, int16_t *output,
1882  int16_t *tmp_buf)
1883 {
1884  int16_t tmp_odd_buf[16 * 8] ALLOC_ALIGNED(ALIGNMENT);
1885  int16_t tmp_eve_buf[16 * 8] ALLOC_ALIGNED(ALIGNMENT);
1886 
1887  vp9_idct8x32_column_even_process_store(input, &tmp_eve_buf[0]);
1888  vp9_idct8x32_column_odd_process_store(input, &tmp_odd_buf[0]);
1889  vp9_idct_butterfly_transpose_store(tmp_buf, &tmp_eve_buf[0],
1890  &tmp_odd_buf[0], output);
1891 }
1892 
1893 static void vp9_idct32x32_1_add_msa(int16_t *input, uint8_t *dst,
1894  int32_t dst_stride)
1895 {
1896  int32_t i;
1897  int16_t out;
1898  v16u8 dst0, dst1, dst2, dst3, tmp0, tmp1, tmp2, tmp3;
1899  v8i16 res0, res1, res2, res3, res4, res5, res6, res7, vec;
1900 
1901  out = ROUND_POWER_OF_TWO((input[0] * cospi_16_64), VP9_DCT_CONST_BITS);
1902  out = ROUND_POWER_OF_TWO((out * cospi_16_64), VP9_DCT_CONST_BITS);
1903  out = ROUND_POWER_OF_TWO(out, 6);
1904 
1905  vec = __msa_fill_h(out);
1906 
1907  for (i = 16; i--;)
1908  {
1909  LD_UB2(dst, 16, dst0, dst1);
1910  LD_UB2(dst + dst_stride, 16, dst2, dst3);
1911 
1912  UNPCK_UB_SH(dst0, res0, res4);
1913  UNPCK_UB_SH(dst1, res1, res5);
1914  UNPCK_UB_SH(dst2, res2, res6);
1915  UNPCK_UB_SH(dst3, res3, res7);
1916  ADD4(res0, vec, res1, vec, res2, vec, res3, vec, res0, res1, res2,
1917  res3);
1918  ADD4(res4, vec, res5, vec, res6, vec, res7, vec, res4, res5, res6,
1919  res7);
1920  CLIP_SH4_0_255(res0, res1, res2, res3);
1921  CLIP_SH4_0_255(res4, res5, res6, res7);
1922  PCKEV_B4_UB(res4, res0, res5, res1, res6, res2, res7, res3,
1923  tmp0, tmp1, tmp2, tmp3);
1924 
1925  ST_UB2(tmp0, tmp1, dst, 16);
1926  dst += dst_stride;
1927  ST_UB2(tmp2, tmp3, dst, 16);
1928  dst += dst_stride;
1929  }
1930 }
1931 
1932 static void vp9_idct32x32_34_colcol_addblk_msa(int16_t *input, uint8_t *dst,
1933  int32_t dst_stride)
1934 {
1935  int32_t i;
1936  int16_t out_arr[32 * 32] ALLOC_ALIGNED(ALIGNMENT);
1937  int16_t *out_ptr = out_arr;
1938  int16_t tmp_buf[8 * 32] ALLOC_ALIGNED(ALIGNMENT);
1939 
1940  for (i = 32; i--;) {
1941  __asm__ volatile (
1942  "sw $zero, (%[out_ptr]) \n\t"
1943  "sw $zero, 4(%[out_ptr]) \n\t"
1944  "sw $zero, 8(%[out_ptr]) \n\t"
1945  "sw $zero, 12(%[out_ptr]) \n\t"
1946  "sw $zero, 16(%[out_ptr]) \n\t"
1947  "sw $zero, 20(%[out_ptr]) \n\t"
1948  "sw $zero, 24(%[out_ptr]) \n\t"
1949  "sw $zero, 28(%[out_ptr]) \n\t"
1950  "sw $zero, 32(%[out_ptr]) \n\t"
1951  "sw $zero, 36(%[out_ptr]) \n\t"
1952  "sw $zero, 40(%[out_ptr]) \n\t"
1953  "sw $zero, 44(%[out_ptr]) \n\t"
1954  "sw $zero, 48(%[out_ptr]) \n\t"
1955  "sw $zero, 52(%[out_ptr]) \n\t"
1956  "sw $zero, 56(%[out_ptr]) \n\t"
1957  "sw $zero, 60(%[out_ptr]) \n\t"
1958 
1959  :
1960  : [out_ptr] "r" (out_ptr)
1961  );
1962 
1963  out_ptr += 32;
1964  }
1965 
1966  out_ptr = out_arr;
1967 
1968  /* process 8*32 block */
1969  vp9_idct8x32_1d_columns_msa(input, out_ptr, &tmp_buf[0]);
1970 
1971  /* transform columns */
1972  for (i = 0; i < 4; i++) {
1973  /* process 8*32 block */
1974  vp9_idct8x32_1d_columns_addblk_msa((out_ptr + (i << 3)),
1975  (dst + (i << 3)), dst_stride);
1976  }
1977 }
1978 
1979 static void vp9_idct32x32_colcol_addblk_msa(int16_t *input, uint8_t *dst,
1980  int32_t dst_stride)
1981 {
1982  int32_t i;
1983  int16_t out_arr[32 * 32] ALLOC_ALIGNED(ALIGNMENT);
1984  int16_t *out_ptr = out_arr;
1985  int16_t tmp_buf[8 * 32] ALLOC_ALIGNED(ALIGNMENT);
1986 
1987  /* transform rows */
1988  for (i = 0; i < 4; i++) {
1989  /* process 8*32 block */
1990  vp9_idct8x32_1d_columns_msa((input + (i << 3)), (out_ptr + (i << 8)),
1991  &tmp_buf[0]);
1992  }
1993 
1994  /* transform columns */
1995  for (i = 0; i < 4; i++) {
1996  /* process 8*32 block */
1997  vp9_idct8x32_1d_columns_addblk_msa((out_ptr + (i << 3)),
1998  (dst + (i << 3)), dst_stride);
1999  }
2000 }
2001 
2002 void ff_idct_idct_4x4_add_msa(uint8_t *dst, ptrdiff_t stride,
2003  int16_t *block, int eob)
2004 {
2005  if (eob > 1) {
2006  vp9_idct4x4_colcol_addblk_msa(block, dst, stride);
2007  memset(block, 0, 4 * 4 * sizeof(*block));
2008  }
2009  else {
2010  vp9_idct4x4_1_add_msa(block, dst, stride);
2011  block[0] = 0;
2012  }
2013 }
2014 
2015 void ff_idct_idct_8x8_add_msa(uint8_t *dst, ptrdiff_t stride,
2016  int16_t *block, int eob)
2017 {
2018  if (eob == 1) {
2019  vp9_idct8x8_1_add_msa(block, dst, stride);
2020  block[0] = 0;
2021  }
2022  else if (eob <= 12) {
2023  vp9_idct8x8_12_colcol_addblk_msa(block, dst, stride);
2024  memset(block, 0, 4 * 8 * sizeof(*block));
2025  }
2026  else {
2027  vp9_idct8x8_colcol_addblk_msa(block, dst, stride);
2028  memset(block, 0, 8 * 8 * sizeof(*block));
2029  }
2030 }
2031 
2032 void ff_idct_idct_16x16_add_msa(uint8_t *dst, ptrdiff_t stride,
2033  int16_t *block, int eob)
2034 {
2035  int i;
2036 
2037  if (eob == 1) {
2038  /* DC only DCT coefficient. */
2039  vp9_idct16x16_1_add_msa(block, dst, stride);
2040  block[0] = 0;
2041  }
2042  else if (eob <= 10) {
2043  vp9_idct16x16_10_colcol_addblk_msa(block, dst, stride);
2044  for (i = 0; i < 4; ++i) {
2045  memset(block, 0, 4 * sizeof(*block));
2046  block += 16;
2047  }
2048  }
2049  else {
2050  vp9_idct16x16_colcol_addblk_msa(block, dst, stride);
2051  memset(block, 0, 16 * 16 * sizeof(*block));
2052  }
2053 }
2054 
2055 void ff_idct_idct_32x32_add_msa(uint8_t *dst, ptrdiff_t stride,
2056  int16_t *block, int eob)
2057 {
2058  int i;
2059 
2060  if (eob == 1) {
2061  vp9_idct32x32_1_add_msa(block, dst, stride);
2062  block[0] = 0;
2063  }
2064  else if (eob <= 34) {
2065  vp9_idct32x32_34_colcol_addblk_msa(block, dst, stride);
2066  for (i = 0; i < 8; ++i) {
2067  memset(block, 0, 8 * sizeof(*block));
2068  block += 32;
2069  }
2070  }
2071  else {
2072  vp9_idct32x32_colcol_addblk_msa(block, dst, stride);
2073  memset(block, 0, 32 * 32 * sizeof(*block));
2074  }
2075 }
2076 
2077 void ff_iadst_iadst_4x4_add_msa(uint8_t *dst, ptrdiff_t stride,
2078  int16_t *block, int eob)
2079 {
2080  vp9_iadst4x4_colcol_addblk_msa(block, dst, stride);
2081  memset(block, 0, 4 * 4 * sizeof(*block));
2082 }
2083 
2084 void ff_iadst_iadst_8x8_add_msa(uint8_t *dst, ptrdiff_t stride,
2085  int16_t *block, int eob)
2086 {
2087  vp9_iadst8x8_colcol_addblk_msa(block, dst, stride);
2088  memset(block, 0, 8 * 8 * sizeof(*block));
2089 }
2090 
2091 void ff_iadst_iadst_16x16_add_msa(uint8_t *dst, ptrdiff_t stride,
2092  int16_t *block, int eob)
2093 {
2094  vp9_iadst16x16_colcol_addblk_msa(block, dst, stride);
2095  memset(block, 0, 16 * 16 * sizeof(*block));
2096 }
2097 
2098 void ff_idct_iadst_4x4_add_msa(uint8_t *dst, ptrdiff_t stride,
2099  int16_t *block, int eob)
2100 {
2101  vp9_idct_iadst_4x4_add_msa(block, dst, stride, eob);
2102  memset(block, 0, 4 * 4 * sizeof(*block));
2103 }
2104 
2105 void ff_idct_iadst_8x8_add_msa(uint8_t *dst, ptrdiff_t stride,
2106  int16_t *block, int eob)
2107 {
2108  vp9_idct_iadst_8x8_add_msa(block, dst, stride, eob);
2109  memset(block, 0, 8 * 8 * sizeof(*block));
2110 }
2111 
2112 void ff_idct_iadst_16x16_add_msa(uint8_t *dst, ptrdiff_t stride,
2113  int16_t *block, int eob)
2114 {
2115  vp9_idct_iadst_16x16_add_msa(block, dst, stride, eob);
2116  memset(block, 0, 16 * 16 * sizeof(*block));
2117 }
2118 
2119 void ff_iadst_idct_4x4_add_msa(uint8_t *dst, ptrdiff_t stride,
2120  int16_t *block, int eob)
2121 {
2122  vp9_iadst_idct_4x4_add_msa(block, dst, stride, eob);
2123  memset(block, 0, 4 * 4 * sizeof(*block));
2124 }
2125 
2126 void ff_iadst_idct_8x8_add_msa(uint8_t *dst, ptrdiff_t stride,
2127  int16_t *block, int eob)
2128 {
2129  vp9_iadst_idct_8x8_add_msa(block, dst, stride, eob);
2130  memset(block, 0, 8 * 8 * sizeof(*block));
2131 }
2132 
2133 void ff_iadst_idct_16x16_add_msa(uint8_t *dst, ptrdiff_t stride,
2134  int16_t *block, int eob)
2135 {
2136  vp9_iadst_idct_16x16_add_msa(block, dst, stride, eob);
2137  memset(block, 0, 16 * 16 * sizeof(*block));
2138 }
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Definition: vp9_idct_msa.c:104
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Definition: vp9_idct_msa.c:2112
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static void vp9_idct4x4_1_add_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:345
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static const int32_t sinpi_1_9
Definition: vp9_idct_msa.c:62
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Definition: generic_macros_msa.h:1490
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static const int32_t cospi_4_64
Definition: vp9_idct_msa.c:32
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static const int32_t sinpi_2_9
Definition: vp9_idct_msa.c:63
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void ff_iadst_iadst_16x16_add_msa(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob)
Definition: vp9_idct_msa.c:2091
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Definition: vp9_idct_msa.c:35
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Definition: generic_macros_msa.h:1029
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Definition: dct.c:113
VP9_DCT_CONST_BITS
#define VP9_DCT_CONST_BITS
Definition: vp9_idct_msa.c:26
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Definition: vp9_idct_msa.c:56
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Definition: vp9_idct_msa.c:116
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Definition: vp9_idct_msa.c:48
uint8_t
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Definition: audio_convert.c:194
ST_SH2
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Definition: generic_macros_msa.h:478
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Definition: generic_macros_msa.h:2325
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Definition: vp9_idct_msa.c:64
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Definition: generic_macros_msa.h:307
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Definition: vp9_idct_msa.c:86
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Definition: generic_macros_msa.h:2202
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Definition: generic_macros_msa.h:1155
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Definition: vp9_idct_msa.c:2105
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static void vp9_iadst4x4_colcol_addblk_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:376
vp9_idct32x32_colcol_addblk_msa
static void vp9_idct32x32_colcol_addblk_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:1979
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Definition: generic_macros_msa.h:1020
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Definition: generic_macros_msa.h:36
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Definition: generic_macros_msa.h:1685
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Definition: vp9_idct_msa.c:594
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Definition: vp9_idct_msa.c:27
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Definition: generic_macros_msa.h:2275
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static void vp9_idct8x32_1d_columns_addblk_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:1869
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#define CLIP_SH2_0_255(in0, in1)
Definition: generic_macros_msa.h:1164
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Definition: generic_macros_msa.h:2368
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void ff_idct_idct_32x32_add_msa(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob)
Definition: vp9_idct_msa.c:2055
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static const int32_t cospi_14_64
Definition: vp9_idct_msa.c:42
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#define ADD4(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3)
Definition: generic_macros_msa.h:2258
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static const int32_t cospi_18_64
Definition: vp9_idct_msa.c:46
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static const int32_t cospi_22_64
Definition: vp9_idct_msa.c:50
vp9_idct_iadst_8x8_add_msa
static void vp9_idct_iadst_8x8_add_msa(int16_t *input, uint8_t *dst, int32_t dst_stride, int32_t eob)
Definition: vp9_idct_msa.c:833
s2
#define s2
Definition: regdef.h:39
vp9_idct_butterfly_transpose_store
static void vp9_idct_butterfly_transpose_store(int16_t *tmp_buf, int16_t *tmp_eve_buf, int16_t *tmp_odd_buf, int16_t *dst)
Definition: vp9_idct_msa.c:1486
ff_iadst_idct_4x4_add_msa
void ff_iadst_idct_4x4_add_msa(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob)
Definition: vp9_idct_msa.c:2119
generic_macros_msa.h
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static const int32_t cospi_9_64
Definition: vp9_idct_msa.c:37
s0
#define s0
Definition: regdef.h:37
zero
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Definition: regdef.h:64
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Definition: generic_macros_msa.h:1538
LD4x4_SH
#define LD4x4_SH(psrc, out0, out1, out2, out3)
Definition: generic_macros_msa.h:416
TRANSPOSE8x8_SH_SH
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Definition: generic_macros_msa.h:2625
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static void vp9_idct32x32_34_colcol_addblk_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:1932
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static const int32_t cospi_5_64
Definition: vp9_idct_msa.c:33
cospi_27_64
static const int32_t cospi_27_64
Definition: vp9_idct_msa.c:55
CLIP_SH4_0_255
#define CLIP_SH4_0_255(in0, in1, in2, in3)
Definition: generic_macros_msa.h:1169
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Definition: regdef.h:42
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Definition: generic_macros_msa.h:398
VP9_IADST8x8_1D
#define VP9_IADST8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7,out0, out1, out2, out3, out4, out5, out6, out7)
Definition: vp9_idct_msa.c:491
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static const int32_t cospi_13_64
Definition: vp9_idct_msa.c:41
SRARI_H2_SH
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Definition: generic_macros_msa.h:2194
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static void vp9_idct16x16_colcol_addblk_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:1207
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static void vp9_idct_iadst_4x4_add_msa(int16_t *input, uint8_t *dst, int32_t dst_stride, int32_t eob)
Definition: vp9_idct_msa.c:410
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static const int32_t cospi_26_64
Definition: vp9_idct_msa.c:54
ALIGNMENT
#define ALIGNMENT
Definition: generic_macros_msa.h:27
vp9_idct8x32_column_butterfly_addblk
static void vp9_idct8x32_column_butterfly_addblk(int16_t *tmp_eve_buf, int16_t *tmp_odd_buf, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:1781
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static const int32_t cospi_21_64
Definition: vp9_idct_msa.c:49
int32_t
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Definition: audio_convert.c:194
PCKEV_H2_SH
#define PCKEV_H2_SH(...)
Definition: generic_macros_msa.h:1918
BUTTERFLY_8
#define BUTTERFLY_8(in0, in1, in2, in3, in4, in5, in6, in7,out0, out1, out2, out3, out4, out5, out6, out7)
Definition: generic_macros_msa.h:2382
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#define SRARI_W2_SW(...)
Definition: generic_macros_msa.h:2219
s4
#define s4
Definition: regdef.h:41
VP9_ADDBLK_ST8x4_UB
#define VP9_ADDBLK_ST8x4_UB(dst, dst_stride, in0, in1, in2, in3)
Definition: vp9_idct_msa.c:229
TRANSPOSE4X8_SH_SH
#define TRANSPOSE4X8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7,out0, out1, out2, out3, out4, out5, out6, out7)
Definition: vp9_idct_msa.c:322
PCKEV_B4_UB
#define PCKEV_B4_UB(...)
Definition: generic_macros_msa.h:1898
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#define s3
Definition: regdef.h:40
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Definition: generic_macros_msa.h:447
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Definition: generic_macros_msa.h:455
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static const int32_t cospi_6_64
Definition: vp9_idct_msa.c:34
VP9_IDCT4x4
#define VP9_IDCT4x4(in0, in1, in2, in3, out0, out1, out2, out3)
Definition: vp9_idct_msa.c:247
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static const int32_t cospi_19_64
Definition: vp9_idct_msa.c:47
cospi_23_64
static const int32_t cospi_23_64
Definition: vp9_idct_msa.c:51
cospi_25_64
static const int32_t cospi_25_64
Definition: vp9_idct_msa.c:53
vp9_iadst_idct_16x16_add_msa
static void vp9_iadst_idct_16x16_add_msa(int16_t *input, uint8_t *dst, int32_t dst_stride, int32_t eob)
Definition: vp9_idct_msa.c:1444
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static const int32_t cospi_8_64
Definition: vp9_idct_msa.c:36
vp9_idct4x4_colcol_addblk_msa
static void vp9_idct4x4_colcol_addblk_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:359
vp9_iadst16x16_colcol_addblk_msa
static void vp9_iadst16x16_colcol_addblk_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:1423
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static void vp9_idct8x32_column_even_process_store(int16_t *tmp_buf, int16_t *tmp_eve_buf)
Definition: vp9_idct_msa.c:1588
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static void vp9_idct16_1d_columns_addblk_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:933
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static void vp9_idct32x32_1_add_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:1893
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static const int32_t cospi_3_64
Definition: vp9_idct_msa.c:31
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static void vp9_iadst_idct_8x8_add_msa(int16_t *input, uint8_t *dst, int32_t dst_stride, int32_t eob)
Definition: vp9_idct_msa.c:808
vp9_iadst16_1d_columns_addblk_msa
static void vp9_iadst16_1d_columns_addblk_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:1257
ST_SH
#define ST_SH(...)
Definition: generic_macros_msa.h:48
VP9_DOTP_CONST_PAIR
#define VP9_DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1)
Definition: vp9_idct_msa.c:67
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static void vp9_iadst8x8_colcol_addblk_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:683
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static const int32_t cospi_16_64
Definition: vp9_idct_msa.c:44
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static const int32_t cospi_1_64
Definition: vp9_idct_msa.c:29
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#define ADD2(in0, in1, in2, in3, out0, out1)
Definition: generic_macros_msa.h:2253
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#define s1
Definition: regdef.h:38
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static const int32_t cospi_31_64
Definition: vp9_idct_msa.c:59
vp9_idct8x8_colcol_addblk_msa
static void vp9_idct8x8_colcol_addblk_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:658
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static const int32_t cospi_10_64
Definition: vp9_idct_msa.c:38
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static void vp9_idct16x16_1_add_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:1133
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static void vp9_idct_iadst_16x16_add_msa(int16_t *input, uint8_t *dst, int32_t dst_stride, int32_t eob)
Definition: vp9_idct_msa.c:1465
stride
GLint GLenum GLboolean GLsizei stride
Definition: opengl_enc.c:105
ST_SH8
#define ST_SH8(...)
Definition: generic_macros_msa.h:499
ILVEV_H2_SH
#define ILVEV_H2_SH(...)
Definition: generic_macros_msa.h:1406
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#define SUB2(in0, in1, in2, in3, out0, out1)
Definition: generic_macros_msa.h:2270
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void ff_idct_idct_16x16_add_msa(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob)
Definition: vp9_idct_msa.c:2032
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static const int32_t cospi_15_64
Definition: vp9_idct_msa.c:43
ALLOC_ALIGNED
#define ALLOC_ALIGNED(align)
Definition: generic_macros_msa.h:28
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static const int32_t cospi_29_64
Definition: vp9_idct_msa.c:57
ILVR_H2_SH
#define ILVR_H2_SH(...)
Definition: generic_macros_msa.h:1588
ff_iadst_iadst_4x4_add_msa
void ff_iadst_iadst_4x4_add_msa(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob)
Definition: vp9_idct_msa.c:2077
LD_SH4
#define LD_SH4(...)
Definition: generic_macros_msa.h:381
vp9_iadst16_1d_columns_msa
static void vp9_iadst16_1d_columns_msa(int16_t *input, int16_t *output)
Definition: vp9_idct_msa.c:1228
LD_UB
#define LD_UB(...)
Definition: generic_macros_msa.h:31
vp9_idct16_1d_columns_msa
static void vp9_idct16_1d_columns_msa(int16_t *input, int16_t *output)
Definition: vp9_idct_msa.c:1033
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static void vp9_idct16x16_10_colcol_addblk_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:1167
VP9_MADD_SHORT
#define VP9_MADD_SHORT(m0, m1, c0, c1, res0, res1)
Definition: vp9_idct_msa.c:184
TRANSPOSE4x4_SH_SH
#define TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, out0, out1, out2, out3)
Definition: generic_macros_msa.h:2586
s6
#define s6
Definition: regdef.h:43
out
FILE * out
Definition: movenc.c:54
VP9_IDCT8x8_1D
#define VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7,out0, out1, out2, out3, out4, out5, out6, out7)
Definition: vp9_idct_msa.c:457
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#define ST8x1_UB(in, pdst)
Definition: generic_macros_msa.h:649
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static void vp9_idct8x8_1_add_msa(int16_t *input, uint8_t *dst, int32_t dst_stride)
Definition: vp9_idct_msa.c:577
ILVR_D2_SH
#define ILVR_D2_SH(...)
Definition: generic_macros_msa.h:1641
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static const int32_t cospi_12_64
Definition: vp9_idct_msa.c:40
ST_SH4
#define ST_SH4(...)
Definition: generic_macros_msa.h:485
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static void vp9_iadst_idct_4x4_add_msa(int16_t *input, uint8_t *dst, int32_t dst_stride, int32_t eob)
Definition: vp9_idct_msa.c:393
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static void vp9_idct8x32_1d_columns_msa(int16_t *input, int16_t *output, int16_t *tmp_buf)
Definition: vp9_idct_msa.c:1881
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#define VP9_MADD_BF(inp0, inp1, inp2, inp3, cst0, cst1, cst2, cst3,out0, out1, out2, out3)
Definition: vp9_idct_msa.c:196
ff_iadst_idct_8x8_add_msa
void ff_iadst_idct_8x8_add_msa(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob)
Definition: vp9_idct_msa.c:2126
VP9_IADST4x4
#define VP9_IADST4x4(in0, in1, in2, in3, out0, out1, out2, out3)
Definition: vp9_idct_msa.c:271
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