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h264pred_mmi.c
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1/*
2 * Loongson SIMD optimized h264pred
3 *
4 * Copyright (c) 2015 Loongson Technology Corporation Limited
5 * Copyright (c) 2015 Zhou Xiaoyong <zhouxiaoyong@loongson.cn>
6 * Zhang Shuangshuang <zhangshuangshuang@ict.ac.cn>
7 *
8 * This file is part of FFmpeg.
9 *
10 * FFmpeg is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
14 *
15 * FFmpeg is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with FFmpeg; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 */
24
25#include "h264pred_mips.h"
26#include "libavcodec/bit_depth_template.c"
27#include "libavutil/intfloat.h"
28#include "libavutil/mips/mmiutils.h"
29#include "constants.h"
30
31void ff_pred16x16_vertical_8_mmi(uint8_t *src, ptrdiff_t stride)
32{
33 double ftmp[2];
34 uint64_t tmp[1];
35 DECLARE_VAR_ALL64;
36
37 __asm__ volatile (
38 "dli %[tmp0], 0x08 \n\t"
39 MMI_LDC1(%[ftmp0], %[srcA], 0x00)
40 MMI_LDC1(%[ftmp1], %[srcA], 0x08)
41
42 "1: \n\t"
43 MMI_SDC1(%[ftmp0], %[src], 0x00)
44 MMI_SDC1(%[ftmp1], %[src], 0x08)
45 PTR_ADDU "%[src], %[src], %[stride] \n\t"
46 MMI_SDC1(%[ftmp0], %[src], 0x00)
47 MMI_SDC1(%[ftmp1], %[src], 0x08)
48
49 "daddi %[tmp0], %[tmp0], -0x01 \n\t"
50 PTR_ADDU "%[src], %[src], %[stride] \n\t"
51 "bnez %[tmp0], 1b \n\t"
52 : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
53 [tmp0]"=&r"(tmp[0]),
54 RESTRICT_ASM_ALL64
55 [src]"+&r"(src)
56 : [stride]"r"((mips_reg)stride), [srcA]"r"((mips_reg)(src-stride))
57 : "memory"
58 );
59}
60
61void ff_pred16x16_horizontal_8_mmi(uint8_t *src, ptrdiff_t stride)
62{
63 uint64_t tmp[3];
64 mips_reg addr[2];
65
66 __asm__ volatile (
67 PTR_ADDI "%[addr0], %[src], -0x01 \n\t"
68 PTR_ADDU "%[addr1], %[src], $0 \n\t"
69 "dli %[tmp2], 0x08 \n\t"
70 "1: \n\t"
71 "lbu %[tmp0], 0x00(%[addr0]) \n\t"
72 "dmul %[tmp1], %[tmp0], %[ff_pb_1] \n\t"
73 "swl %[tmp1], 0x07(%[addr1]) \n\t"
74 "swr %[tmp1], 0x00(%[addr1]) \n\t"
75 "swl %[tmp1], 0x0f(%[addr1]) \n\t"
76 "swr %[tmp1], 0x08(%[addr1]) \n\t"
77 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
78 PTR_ADDU "%[addr1], %[addr1], %[stride] \n\t"
79 "lbu %[tmp0], 0x00(%[addr0]) \n\t"
80 "dmul %[tmp1], %[tmp0], %[ff_pb_1] \n\t"
81 "swl %[tmp1], 0x07(%[addr1]) \n\t"
82 "swr %[tmp1], 0x00(%[addr1]) \n\t"
83 "swl %[tmp1], 0x0f(%[addr1]) \n\t"
84 "swr %[tmp1], 0x08(%[addr1]) \n\t"
85 "daddi %[tmp2], %[tmp2], -0x01 \n\t"
86 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
87 PTR_ADDU "%[addr1], %[addr1], %[stride] \n\t"
88 "bnez %[tmp2], 1b \n\t"
89 : [tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]),
90 [tmp2]"=&r"(tmp[2]),
91 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1])
92 : [src]"r"((mips_reg)src), [stride]"r"((mips_reg)stride),
93 [ff_pb_1]"r"(ff_pb_1)
94 : "memory"
95 );
96}
97
98void ff_pred16x16_dc_8_mmi(uint8_t *src, ptrdiff_t stride)
99{
100 uint64_t tmp[4];
101 mips_reg addr[2];
102
103 __asm__ volatile (
104 PTR_ADDI "%[addr0], %[src], -0x01 \n\t"
105 "dli %[tmp0], 0x08 \n\t"
106 "xor %[tmp3], %[tmp3], %[tmp3] \n\t"
107 "1: \n\t"
108 "lbu %[tmp1], 0x00(%[addr0]) \n\t"
109 "daddu %[tmp3], %[tmp3], %[tmp1] \n\t"
110 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
111 "lbu %[tmp1], 0x00(%[addr0]) \n\t"
112 "daddi %[tmp0], %[tmp0], -0x01 \n\t"
113 "daddu %[tmp3], %[tmp3], %[tmp1] \n\t"
114 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
115 "bnez %[tmp0], 1b \n\t"
116
117 "dli %[tmp0], 0x08 \n\t"
118 PTR_SUBU "%[addr0], %[src], %[stride] \n\t"
119 "2: \n\t"
120 "lbu %[tmp1], 0x00(%[addr0]) \n\t"
121 "daddu %[tmp3], %[tmp3], %[tmp1] \n\t"
122 PTR_ADDIU "%[addr0], %[addr0], 0x01 \n\t"
123 "lbu %[tmp1], 0x00(%[addr0]) \n\t"
124 "daddi %[tmp0], %[tmp0], -0x01 \n\t"
125 "daddu %[tmp3], %[tmp3], %[tmp1] \n\t"
126 PTR_ADDIU "%[addr0], %[addr0], 0x01 \n\t"
127 "bnez %[tmp0], 2b \n\t"
128
129 "daddiu %[tmp3], %[tmp3], 0x10 \n\t"
130 "dsra %[tmp3], 0x05 \n\t"
131 "dmul %[tmp2], %[tmp3], %[ff_pb_1] \n\t"
132 PTR_ADDU "%[addr0], %[src], $0 \n\t"
133 "dli %[tmp0], 0x08 \n\t"
134 "3: \n\t"
135 "swl %[tmp2], 0x07(%[addr0]) \n\t"
136 "swr %[tmp2], 0x00(%[addr0]) \n\t"
137 "swl %[tmp2], 0x0f(%[addr0]) \n\t"
138 "swr %[tmp2], 0x08(%[addr0]) \n\t"
139 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
140 "swl %[tmp2], 0x07(%[addr0]) \n\t"
141 "swr %[tmp2], 0x00(%[addr0]) \n\t"
142 "swl %[tmp2], 0x0f(%[addr0]) \n\t"
143 "swr %[tmp2], 0x08(%[addr0]) \n\t"
144 "daddi %[tmp0], %[tmp0], -0x01 \n\t"
145 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
146 "bnez %[tmp0], 3b \n\t"
147 : [tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]),
148 [tmp2]"=&r"(tmp[2]), [tmp3]"=&r"(tmp[3]),
149 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1])
150 : [src]"r"((mips_reg)src), [stride]"r"((mips_reg)stride),
151 [ff_pb_1]"r"(ff_pb_1)
152 : "memory"
153 );
154}
155
156void ff_pred8x8l_top_dc_8_mmi(uint8_t *src, int has_topleft,
157 int has_topright, ptrdiff_t stride)
158{
159 double ftmp[11];
160 mips_reg tmp[3];
161 union av_intfloat64 dc;
162 DECLARE_VAR_ALL64;
163 DECLARE_VAR_ADDRT;
164
165 __asm__ volatile (
166 "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
167 MMI_ULDC1(%[ftmp10], %[srcA], 0x00)
168 MMI_ULDC1(%[ftmp9], %[src0], 0x00)
169 MMI_ULDC1(%[ftmp8], %[src1], 0x00)
170
171 "punpcklbh %[ftmp7], %[ftmp10], %[ftmp0] \n\t"
172 "punpckhbh %[ftmp6], %[ftmp10], %[ftmp0] \n\t"
173 "punpcklbh %[ftmp5], %[ftmp9], %[ftmp0] \n\t"
174 "punpckhbh %[ftmp4], %[ftmp9], %[ftmp0] \n\t"
175 "punpcklbh %[ftmp3], %[ftmp8], %[ftmp0] \n\t"
176 "punpckhbh %[ftmp2], %[ftmp8], %[ftmp0] \n\t"
177 "bnez %[has_topleft], 1f \n\t"
178 "pinsrh_0 %[ftmp7], %[ftmp7], %[ftmp5] \n\t"
179
180 "1: \n\t"
181 "bnez %[has_topright], 2f \n\t"
182 "dli %[tmp0], 0xa4 \n\t"
183 "mtc1 %[tmp0], %[ftmp1] \n\t"
184 "pshufh %[ftmp2], %[ftmp2], %[ftmp1] \n\t"
185
186 "2: \n\t"
187 "dli %[tmp0], 0x02 \n\t"
188 "mtc1 %[tmp0], %[ftmp1] \n\t"
189 "pmullh %[ftmp5], %[ftmp5], %[ff_pw_2] \n\t"
190 "pmullh %[ftmp4], %[ftmp4], %[ff_pw_2] \n\t"
191 "paddh %[ftmp7], %[ftmp7], %[ftmp5] \n\t"
192 "paddh %[ftmp6], %[ftmp6], %[ftmp4] \n\t"
193 "paddh %[ftmp7], %[ftmp7], %[ftmp3] \n\t"
194 "paddh %[ftmp6], %[ftmp6], %[ftmp2] \n\t"
195 "paddh %[ftmp7], %[ftmp7], %[ff_pw_2] \n\t"
196 "paddh %[ftmp6], %[ftmp6], %[ff_pw_2] \n\t"
197 "psrah %[ftmp7], %[ftmp7], %[ftmp1] \n\t"
198 "psrah %[ftmp6], %[ftmp6], %[ftmp1] \n\t"
199 "packushb %[ftmp9], %[ftmp7], %[ftmp6] \n\t"
200 "biadd %[ftmp10], %[ftmp9] \n\t"
201 "mfc1 %[tmp1], %[ftmp10] \n\t"
202 "addiu %[tmp1], %[tmp1], 0x04 \n\t"
203 "srl %[tmp1], %[tmp1], 0x03 \n\t"
204 "mul %[dc], %[tmp1], %[ff_pb_1] \n\t"
205 : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
206 [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
207 [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
208 [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
209 [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
210 [ftmp10]"=&f"(ftmp[10]),
211 [tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]),
212 RESTRICT_ASM_ALL64
213 [dc]"=r"(dc.i)
214 : [srcA]"r"((mips_reg)(src-stride-1)),
215 [src0]"r"((mips_reg)(src-stride)),
216 [src1]"r"((mips_reg)(src-stride+1)),
217 [has_topleft]"r"(has_topleft), [has_topright]"r"(has_topright),
218 [ff_pb_1]"r"(ff_pb_1.i), [ff_pw_2]"f"(ff_pw_2.f)
219 : "memory"
220 );
221
222 __asm__ volatile (
223 "dli %[tmp0], 0x02 \n\t"
224 "punpcklwd %[ftmp0], %[dc], %[dc] \n\t"
225
226 "1: \n\t"
227 MMI_SDC1(%[ftmp0], %[src], 0x00)
228 MMI_SDXC1(%[ftmp0], %[src], %[stride], 0x00)
229 PTR_ADDU "%[src], %[src], %[stride] \n\t"
230 PTR_ADDU "%[src], %[src], %[stride] \n\t"
231 MMI_SDC1(%[ftmp0], %[src], 0x00)
232 MMI_SDXC1(%[ftmp0], %[src], %[stride], 0x00)
233
234 "daddi %[tmp0], %[tmp0], -0x01 \n\t"
235 PTR_ADDU "%[src], %[src], %[stride] \n\t"
236 PTR_ADDU "%[src], %[src], %[stride] \n\t"
237 "bnez %[tmp0], 1b \n\t"
238 : [ftmp0]"=&f"(ftmp[0]), [tmp0]"=&r"(tmp[0]),
239 RESTRICT_ASM_ALL64
240 RESTRICT_ASM_ADDRT
241 [src]"+&r"(src)
242 : [dc]"f"(dc.f), [stride]"r"((mips_reg)stride)
243 : "memory"
244 );
245}
246
247void ff_pred8x8l_dc_8_mmi(uint8_t *src, int has_topleft, int has_topright,
248 ptrdiff_t stride)
249{
250 uint32_t dc1, dc2;
251 double ftmp[14];
252 mips_reg tmp[1];
253 union av_intfloat64 dc;
254
255 const int l0 = ((has_topleft ? src[-1+-1*stride] : src[-1+0*stride]) + 2*src[-1+0*stride] + src[-1+1*stride] + 2) >> 2;
256 const int l1 = (src[-1+0*stride] + 2*src[-1+1*stride] + src[-1+2*stride] + 2) >> 2;
257 const int l2 = (src[-1+1*stride] + 2*src[-1+2*stride] + src[-1+3*stride] + 2) >> 2;
258 const int l3 = (src[-1+2*stride] + 2*src[-1+3*stride] + src[-1+4*stride] + 2) >> 2;
259 const int l4 = (src[-1+3*stride] + 2*src[-1+4*stride] + src[-1+5*stride] + 2) >> 2;
260 const int l5 = (src[-1+4*stride] + 2*src[-1+5*stride] + src[-1+6*stride] + 2) >> 2;
261 const int l6 = (src[-1+5*stride] + 2*src[-1+6*stride] + src[-1+7*stride] + 2) >> 2;
262 const int l7 = (src[-1+6*stride] + 2*src[-1+7*stride] + src[-1+7*stride] + 2) >> 2;
263
264 DECLARE_VAR_ALL64;
265 DECLARE_VAR_ADDRT;
266
267 __asm__ volatile (
268 MMI_ULDC1(%[ftmp4], %[srcA], 0x00)
269 MMI_ULDC1(%[ftmp5], %[src0], 0x00)
270 MMI_ULDC1(%[ftmp6], %[src1], 0x00)
271 "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
272 "dli %[tmp0], 0x03 \n\t"
273 "punpcklbh %[ftmp7], %[ftmp4], %[ftmp0] \n\t"
274 "punpckhbh %[ftmp8], %[ftmp4], %[ftmp0] \n\t"
275 "mtc1 %[tmp0], %[ftmp1] \n\t"
276 "punpcklbh %[ftmp9], %[ftmp5], %[ftmp0] \n\t"
277 "punpckhbh %[ftmp10], %[ftmp5], %[ftmp0] \n\t"
278 "punpcklbh %[ftmp11], %[ftmp6], %[ftmp0] \n\t"
279 "punpckhbh %[ftmp12], %[ftmp6], %[ftmp0] \n\t"
280 "pshufh %[ftmp3], %[ftmp8], %[ftmp1] \n\t"
281 "pshufh %[ftmp13], %[ftmp12], %[ftmp1] \n\t"
282 "pinsrh_3 %[ftmp8], %[ftmp8], %[ftmp13] \n\t"
283 "pinsrh_3 %[ftmp12], %[ftmp12], %[ftmp3] \n\t"
284 "bnez %[has_topleft], 1f \n\t"
285 "pinsrh_0 %[ftmp7], %[ftmp7], %[ftmp9] \n\t"
286
287 "1: \n\t"
288 "bnez %[has_topright], 2f \n\t"
289 "pshufh %[ftmp13], %[ftmp10], %[ftmp1] \n\t"
290 "pinsrh_3 %[ftmp8], %[ftmp8], %[ftmp13] \n\t"
291
292 "2: \n\t"
293 "dli %[tmp0], 0x02 \n\t"
294 "mtc1 %[tmp0], %[ftmp1] \n\t"
295 "pshufh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
296 "pmullh %[ftmp9], %[ftmp9], %[ftmp2] \n\t"
297 "pmullh %[ftmp10], %[ftmp10], %[ftmp2] \n\t"
298 "paddh %[ftmp7], %[ftmp7], %[ftmp9] \n\t"
299 "paddh %[ftmp8], %[ftmp8], %[ftmp10] \n\t"
300 "paddh %[ftmp7], %[ftmp7], %[ftmp11] \n\t"
301 "paddh %[ftmp8], %[ftmp8], %[ftmp12] \n\t"
302 "paddh %[ftmp7], %[ftmp7], %[ftmp2] \n\t"
303 "paddh %[ftmp8], %[ftmp8], %[ftmp2] \n\t"
304 "psrah %[ftmp7], %[ftmp7], %[ftmp1] \n\t"
305 "psrah %[ftmp8], %[ftmp8], %[ftmp1] \n\t"
306 "packushb %[ftmp5], %[ftmp7], %[ftmp8] \n\t"
307 "biadd %[ftmp4], %[ftmp5] \n\t"
308 "mfc1 %[dc2], %[ftmp4] \n\t"
309 : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
310 [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
311 [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
312 [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
313 [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
314 [ftmp10]"=&f"(ftmp[10]), [ftmp11]"=&f"(ftmp[11]),
315 [ftmp12]"=&f"(ftmp[12]), [ftmp13]"=&f"(ftmp[13]),
316 [tmp0]"=&r"(tmp[0]),
317 RESTRICT_ASM_ALL64
318 [dc2]"=r"(dc2)
319 : [srcA]"r"((mips_reg)(src-stride-1)),
320 [src0]"r"((mips_reg)(src-stride)),
321 [src1]"r"((mips_reg)(src-stride+1)),
322 [has_topleft]"r"(has_topleft), [has_topright]"r"(has_topright)
323 : "memory"
324 );
325
326 dc1 = l0+l1+l2+l3+l4+l5+l6+l7;
327 dc.i = ((dc1+dc2+8)>>4)*0x01010101U;
328
329 __asm__ volatile (
330 "dli %[tmp0], 0x02 \n\t"
331 "punpcklwd %[ftmp0], %[dc], %[dc] \n\t"
332
333 "1: \n\t"
334 MMI_SDC1(%[ftmp0], %[src], 0x00)
335 MMI_SDXC1(%[ftmp0], %[src], %[stride], 0x00)
336 PTR_ADDU "%[src], %[src], %[stride] \n\t"
337 PTR_ADDU "%[src], %[src], %[stride] \n\t"
338 MMI_SDC1(%[ftmp0], %[src], 0x00)
339 MMI_SDXC1(%[ftmp0], %[src], %[stride], 0x00)
340
341 "daddi %[tmp0], %[tmp0], -0x01 \n\t"
342 PTR_ADDU "%[src], %[src], %[stride] \n\t"
343 PTR_ADDU "%[src], %[src], %[stride] \n\t"
344 "bnez %[tmp0], 1b \n\t"
345 : [ftmp0]"=&f"(ftmp[0]), [tmp0]"=&r"(tmp[0]),
346 RESTRICT_ASM_ALL64
347 RESTRICT_ASM_ADDRT
348 [src]"+&r"(src)
349 : [dc]"f"(dc.f), [stride]"r"((mips_reg)stride)
350 : "memory"
351 );
352}
353
354void ff_pred8x8l_vertical_8_mmi(uint8_t *src, int has_topleft,
355 int has_topright, ptrdiff_t stride)
356{
357 double ftmp[12];
358 mips_reg tmp[1];
359 DECLARE_VAR_ALL64;
360
361 __asm__ volatile (
362 "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
363 MMI_LDC1(%[ftmp3], %[srcA], 0x00)
364 MMI_LDC1(%[ftmp4], %[src0], 0x00)
365 MMI_LDC1(%[ftmp5], %[src1], 0x00)
366 "punpcklbh %[ftmp6], %[ftmp3], %[ftmp0] \n\t"
367 "punpckhbh %[ftmp7], %[ftmp3], %[ftmp0] \n\t"
368 "punpcklbh %[ftmp8], %[ftmp4], %[ftmp0] \n\t"
369 "punpckhbh %[ftmp9], %[ftmp4], %[ftmp0] \n\t"
370 "punpcklbh %[ftmp10], %[ftmp5], %[ftmp0] \n\t"
371 "punpckhbh %[ftmp11], %[ftmp5], %[ftmp0] \n\t"
372 "bnez %[has_topleft], 1f \n\t"
373 "pinsrh_0 %[ftmp6], %[ftmp6], %[ftmp8] \n\t"
374
375 "1: \n\t"
376 "bnez %[has_topright], 2f \n\t"
377 "dli %[tmp0], 0xa4 \n\t"
378 "mtc1 %[tmp0], %[ftmp1] \n\t"
379 "pshufh %[ftmp11], %[ftmp11], %[ftmp1] \n\t"
380
381 "2: \n\t"
382 "dli %[tmp0], 0x02 \n\t"
383 "mtc1 %[tmp0], %[ftmp1] \n\t"
384 "pshufh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
385 "pmullh %[ftmp8], %[ftmp8], %[ftmp2] \n\t"
386 "pmullh %[ftmp9], %[ftmp9], %[ftmp2] \n\t"
387 "paddh %[ftmp6], %[ftmp6], %[ftmp8] \n\t"
388 "paddh %[ftmp7], %[ftmp7], %[ftmp9] \n\t"
389 "paddh %[ftmp6], %[ftmp6], %[ftmp10] \n\t"
390 "paddh %[ftmp7], %[ftmp7], %[ftmp11] \n\t"
391 "paddh %[ftmp6], %[ftmp6], %[ftmp2] \n\t"
392 "paddh %[ftmp7], %[ftmp7], %[ftmp2] \n\t"
393 "psrah %[ftmp6], %[ftmp6], %[ftmp1] \n\t"
394 "psrah %[ftmp7], %[ftmp7], %[ftmp1] \n\t"
395 "packushb %[ftmp4], %[ftmp6], %[ftmp7] \n\t"
396 MMI_SDC1(%[ftmp4], %[src], 0x00)
397 : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
398 [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
399 [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
400 [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
401 [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
402 [ftmp10]"=&f"(ftmp[10]), [ftmp11]"=&f"(ftmp[11]),
403 [tmp0]"=&r"(tmp[0]),
404 RESTRICT_ASM_ALL64
405 [src]"=r"(src)
406 : [srcA]"r"((mips_reg)(src-stride-1)),
407 [src0]"r"((mips_reg)(src-stride)),
408 [src1]"r"((mips_reg)(src-stride+1)),
409 [has_topleft]"r"(has_topleft), [has_topright]"r"(has_topright)
410 : "memory"
411 );
412
413 __asm__ volatile (
414 "dli %[tmp0], 0x02 \n\t"
415
416 "1: \n\t"
417 MMI_SDC1(%[ftmp0], %[src], 0x00)
418 PTR_ADDU "%[src], %[src], %[stride] \n\t"
419 MMI_SDC1(%[ftmp0], %[src], 0x00)
420 PTR_ADDU "%[src], %[src], %[stride] \n\t"
421 MMI_SDC1(%[ftmp0], %[src], 0x00)
422 PTR_ADDU "%[src], %[src], %[stride] \n\t"
423 MMI_SDC1(%[ftmp0], %[src], 0x00)
424
425 "daddi %[tmp0], %[tmp0], -0x01 \n\t"
426 PTR_ADDU "%[src], %[src], %[stride] \n\t"
427 "bnez %[tmp0], 1b \n\t"
428 : [ftmp0]"=&f"(ftmp[0]), [tmp0]"=&r"(tmp[0]),
429 RESTRICT_ASM_ALL64
430 [src]"+&r"(src)
431 : [stride]"r"((mips_reg)stride)
432 : "memory"
433 );
434}
435
436void ff_pred4x4_dc_8_mmi(uint8_t *src, const uint8_t *topright,
437 ptrdiff_t stride)
438{
439 const int dc = (src[-stride] + src[1-stride] + src[2-stride]
440 + src[3-stride] + src[-1+0*stride] + src[-1+1*stride]
441 + src[-1+2*stride] + src[-1+3*stride] + 4) >>3;
442 uint64_t tmp[2];
443 mips_reg addr[1];
444 DECLARE_VAR_ADDRT;
445
446 __asm__ volatile (
447 PTR_ADDU "%[tmp0], %[dc], $0 \n\t"
448 "dmul %[tmp1], %[tmp0], %[ff_pb_1] \n\t"
449 "xor %[addr0], %[addr0], %[addr0] \n\t"
450 MMI_SWX(%[tmp1], %[src], %[addr0], 0x00)
451 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
452 MMI_SWX(%[tmp1], %[src], %[addr0], 0x00)
453 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
454 MMI_SWX(%[tmp1], %[src], %[addr0], 0x00)
455 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
456 MMI_SWX(%[tmp1], %[src], %[addr0], 0x00)
457 : [tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]),
458 RESTRICT_ASM_ADDRT
459 [addr0]"=&r"(addr[0])
460 : [src]"r"((mips_reg)src), [stride]"r"((mips_reg)stride),
461 [dc]"r"(dc), [ff_pb_1]"r"(ff_pb_1)
462 : "memory"
463 );
464}
465
466void ff_pred8x8_vertical_8_mmi(uint8_t *src, ptrdiff_t stride)
467{
468 uint64_t tmp[2];
469 mips_reg addr[2];
470
471 __asm__ volatile (
472 PTR_SUBU "%[addr0], %[src], %[stride] \n\t"
473 PTR_ADDU "%[addr1], %[src], $0 \n\t"
474 "ldl %[tmp0], 0x07(%[addr0]) \n\t"
475 "ldr %[tmp0], 0x00(%[addr0]) \n\t"
476 "dli %[tmp1], 0x04 \n\t"
477 "1: \n\t"
478 "sdl %[tmp0], 0x07(%[addr1]) \n\t"
479 "sdr %[tmp0], 0x00(%[addr1]) \n\t"
480 PTR_ADDU "%[addr1], %[stride] \n\t"
481 "sdl %[tmp0], 0x07(%[addr1]) \n\t"
482 "sdr %[tmp0], 0x00(%[addr1]) \n\t"
483 "daddi %[tmp1], -0x01 \n\t"
484 PTR_ADDU "%[addr1], %[stride] \n\t"
485 "bnez %[tmp1], 1b \n\t"
486 : [tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]),
487 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1])
488 : [src]"r"((mips_reg)src), [stride]"r"((mips_reg)stride)
489 : "memory"
490 );
491}
492
493void ff_pred8x8_horizontal_8_mmi(uint8_t *src, ptrdiff_t stride)
494{
495 uint64_t tmp[3];
496 mips_reg addr[2];
497
498 __asm__ volatile (
499 PTR_ADDI "%[addr0], %[src], -0x01 \n\t"
500 PTR_ADDU "%[addr1], %[src], $0 \n\t"
501 "dli %[tmp0], 0x04 \n\t"
502 "1: \n\t"
503 "lbu %[tmp1], 0x00(%[addr0]) \n\t"
504 "dmul %[tmp2], %[tmp1], %[ff_pb_1] \n\t"
505 "swl %[tmp2], 0x07(%[addr1]) \n\t"
506 "swr %[tmp2], 0x00(%[addr1]) \n\t"
507 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
508 PTR_ADDU "%[addr1], %[addr1], %[stride] \n\t"
509 "lbu %[tmp1], 0x00(%[addr0]) \n\t"
510 "dmul %[tmp2], %[tmp1], %[ff_pb_1] \n\t"
511 "swl %[tmp2], 0x07(%[addr1]) \n\t"
512 "swr %[tmp2], 0x00(%[addr1]) \n\t"
513 "daddi %[tmp0], %[tmp0], -0x01 \n\t"
514 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
515 PTR_ADDU "%[addr1], %[addr1], %[stride] \n\t"
516 "bnez %[tmp0], 1b \n\t"
517 : [tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]),
518 [tmp2]"=&r"(tmp[2]),
519 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1])
520 : [src]"r"((mips_reg)src), [stride]"r"((mips_reg)stride),
521 [ff_pb_1]"r"(ff_pb_1)
522 : "memory"
523 );
524}
525
526void ff_pred8x8_top_dc_8_mmi(uint8_t *src, ptrdiff_t stride)
527{
528 double ftmp[4];
529 uint64_t tmp[1];
530 mips_reg addr[1];
531 DECLARE_VAR_ALL64;
532
533 __asm__ volatile (
534 "dli %[tmp0], 0x02 \n\t"
535 "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
536 PTR_SUBU "%[addr0], %[src], %[stride] \n\t"
537 MMI_LDC1(%[ftmp1], %[addr0], 0x00)
538 "punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
539 "punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
540 "biadd %[ftmp2], %[ftmp2] \n\t"
541 "biadd %[ftmp3], %[ftmp3] \n\t"
542 "mtc1 %[tmp0], %[ftmp1] \n\t"
543 "pshufh %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
544 "pshufh %[ftmp3], %[ftmp3], %[ftmp0] \n\t"
545 "pshufh %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
546 "paddush %[ftmp2], %[ftmp2], %[ftmp1] \n\t"
547 "paddush %[ftmp3], %[ftmp3], %[ftmp1] \n\t"
548 "mtc1 %[tmp0], %[ftmp1] \n\t"
549 "psrlh %[ftmp2], %[ftmp2], %[ftmp1] \n\t"
550 "psrlh %[ftmp3], %[ftmp3], %[ftmp1] \n\t"
551 "packushb %[ftmp1], %[ftmp2], %[ftmp3] \n\t"
552 MMI_SDC1(%[ftmp1], %[src], 0x00)
553 PTR_ADDU "%[src], %[src], %[stride] \n\t"
554 MMI_SDC1(%[ftmp1], %[src], 0x00)
555 PTR_ADDU "%[src], %[src], %[stride] \n\t"
556 MMI_SDC1(%[ftmp1], %[src], 0x00)
557 PTR_ADDU "%[src], %[src], %[stride] \n\t"
558 MMI_SDC1(%[ftmp1], %[src], 0x00)
559 PTR_ADDU "%[src], %[src], %[stride] \n\t"
560 MMI_SDC1(%[ftmp1], %[src], 0x00)
561 PTR_ADDU "%[src], %[src], %[stride] \n\t"
562 MMI_SDC1(%[ftmp1], %[src], 0x00)
563 PTR_ADDU "%[src], %[src], %[stride] \n\t"
564 MMI_SDC1(%[ftmp1], %[src], 0x00)
565 PTR_ADDU "%[src], %[src], %[stride] \n\t"
566 MMI_SDC1(%[ftmp1], %[src], 0x00)
567 : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
568 [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
569 [tmp0]"=&r"(tmp[0]),
570 RESTRICT_ASM_ALL64
571 [addr0]"=&r"(addr[0]),
572 [src]"+&r"(src)
573 : [stride]"r"((mips_reg)stride)
574 : "memory"
575 );
576}
577
578void ff_pred8x8_dc_8_mmi(uint8_t *src, ptrdiff_t stride)
579{
580 double ftmp[5];
581 mips_reg addr[7];
582
583 __asm__ volatile (
584 "negu %[addr0], %[stride] \n\t"
585 PTR_ADDU "%[addr0], %[addr0], %[src] \n\t"
586 PTR_ADDIU "%[addr1], %[addr0], 0x04 \n\t"
587 "lbu %[addr2], 0x00(%[addr0]) \n\t"
588 PTR_ADDU "%[addr3], $0, %[addr2] \n\t"
589 PTR_ADDIU "%[addr0], 0x01 \n\t"
590 "lbu %[addr2], 0x00(%[addr1]) \n\t"
591 PTR_ADDU "%[addr4], $0, %[addr2] \n\t"
592 PTR_ADDIU "%[addr1], 0x01 \n\t"
593 "lbu %[addr2], 0x00(%[addr0]) \n\t"
594 PTR_ADDU "%[addr3], %[addr3], %[addr2] \n\t"
595 PTR_ADDIU "%[addr0], 0x01 \n\t"
596 "lbu %[addr2], 0x00(%[addr1]) \n\t"
597 PTR_ADDU "%[addr4], %[addr4], %[addr2] \n\t"
598 PTR_ADDIU "%[addr1], 0x01 \n\t"
599 "lbu %[addr2], 0x00(%[addr0]) \n\t"
600 PTR_ADDU "%[addr3], %[addr3], %[addr2] \n\t"
601 PTR_ADDIU "%[addr0], 0x01 \n\t"
602 "lbu %[addr2], 0x00(%[addr1]) \n\t"
603 PTR_ADDU "%[addr4], %[addr4], %[addr2] \n\t"
604 PTR_ADDIU "%[addr1], 0x01 \n\t"
605 "lbu %[addr2], 0x00(%[addr0]) \n\t"
606 PTR_ADDU "%[addr3], %[addr3], %[addr2] \n\t"
607 PTR_ADDIU "%[addr0], 0x01 \n\t"
608 "lbu %[addr2], 0x00(%[addr1]) \n\t"
609 PTR_ADDU "%[addr4], %[addr4], %[addr2] \n\t"
610 PTR_ADDIU "%[addr1], 0x01 \n\t"
611 "dli %[addr2], -0x01 \n\t"
612 PTR_ADDU "%[addr2], %[addr2], %[src] \n\t"
613 "lbu %[addr1], 0x00(%[addr2]) \n\t"
614 PTR_ADDU "%[addr5], $0, %[addr1] \n\t"
615 PTR_ADDU "%[addr2], %[addr2], %[stride] \n\t"
616 "lbu %[addr1], 0x00(%[addr2]) \n\t"
617 PTR_ADDU "%[addr5], %[addr5], %[addr1] \n\t"
618 PTR_ADDU "%[addr2], %[addr2], %[stride] \n\t"
619 "lbu %[addr1], 0x00(%[addr2]) \n\t"
620 PTR_ADDU "%[addr5], %[addr5], %[addr1] \n\t"
621 PTR_ADDU "%[addr2], %[addr2], %[stride] \n\t"
622 "lbu %[addr1], 0x00(%[addr2]) \n\t"
623 PTR_ADDU "%[addr5], %[addr5], %[addr1] \n\t"
624 PTR_ADDU "%[addr2], %[addr2], %[stride] \n\t"
625 "lbu %[addr1], 0x00(%[addr2]) \n\t"
626 PTR_ADDU "%[addr6], $0, %[addr1] \n\t"
627 PTR_ADDU "%[addr2], %[addr2], %[stride] \n\t"
628 "lbu %[addr1], 0x00(%[addr2]) \n\t"
629 PTR_ADDU "%[addr6], %[addr6], %[addr1] \n\t"
630 PTR_ADDU "%[addr2], %[addr2], %[stride] \n\t"
631 "lbu %[addr1], 0x00(%[addr2]) \n\t"
632 PTR_ADDU "%[addr6], %[addr6], %[addr1] \n\t"
633 PTR_ADDU "%[addr2], %[addr2], %[stride] \n\t"
634 "lbu %[addr1], 0x00(%[addr2]) \n\t"
635 PTR_ADDU "%[addr6], %[addr6], %[addr1] \n\t"
636 PTR_ADDU "%[addr3], %[addr3], %[addr5] \n\t"
637 PTR_ADDIU "%[addr3], %[addr3], 0x04 \n\t"
638 PTR_ADDIU "%[addr4], %[addr4], 0x02 \n\t"
639 PTR_ADDIU "%[addr1], %[addr6], 0x02 \n\t"
640 PTR_ADDU "%[addr2], %[addr4], %[addr1] \n\t"
641 PTR_SRL "%[addr3], 0x03 \n\t"
642 PTR_SRL "%[addr4], 0x02 \n\t"
643 PTR_SRL "%[addr1], 0x02 \n\t"
644 PTR_SRL "%[addr2], 0x03 \n\t"
645 "pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
646 "dmtc1 %[addr3], %[ftmp1] \n\t"
647 "pshufh %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
648 "dmtc1 %[addr4], %[ftmp2] \n\t"
649 "pshufh %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
650 "dmtc1 %[addr1], %[ftmp3] \n\t"
651 "pshufh %[ftmp3], %[ftmp3], %[ftmp0] \n\t"
652 "dmtc1 %[addr2], %[ftmp4] \n\t"
653 "pshufh %[ftmp4], %[ftmp4], %[ftmp0] \n\t"
654 "packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
655 "packushb %[ftmp2], %[ftmp3], %[ftmp4] \n\t"
656 PTR_ADDU "%[addr0], $0, %[src] \n\t"
657 MMI_SDC1(%[ftmp1], %[addr0], 0x00)
658 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
659 MMI_SDC1(%[ftmp1], %[addr0], 0x00)
660 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
661 MMI_SDC1(%[ftmp1], %[addr0], 0x00)
662 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
663 MMI_SDC1(%[ftmp1], %[addr0], 0x00)
664 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
665 MMI_SDC1(%[ftmp2], %[addr0], 0x00)
666 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
667 MMI_SDC1(%[ftmp2], %[addr0], 0x00)
668 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
669 MMI_SDC1(%[ftmp2], %[addr0], 0x00)
670 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
671 MMI_SDC1(%[ftmp2], %[addr0], 0x00)
672 : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
673 [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
674 [ftmp4]"=&f"(ftmp[4]),
675 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
676 [addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]),
677 [addr4]"=&r"(addr[4]), [addr5]"=&r"(addr[5]),
678 [addr6]"=&r"(addr[6])
679 : [src]"r"((mips_reg)src), [stride]"r"((mips_reg)stride)
680 : "memory"
681 );
682}
683
684void ff_pred8x16_vertical_8_mmi(uint8_t *src, ptrdiff_t stride)
685{
686 double ftmp[1];
687 uint64_t tmp[1];
688 DECLARE_VAR_ALL64;
689
690 __asm__ volatile (
691 MMI_LDC1(%[ftmp0], %[srcA], 0x00)
692 "dli %[tmp0], 0x04 \n\t"
693
694 "1: \n\t"
695 MMI_SDC1(%[ftmp0], %[src], 0x00)
696 PTR_ADDU "%[src], %[src], %[stride] \n\t"
697 MMI_SDC1(%[ftmp0], %[src], 0x00)
698 PTR_ADDU "%[src], %[src], %[stride] \n\t"
699 MMI_SDC1(%[ftmp0], %[src], 0x00)
700 PTR_ADDU "%[src], %[src], %[stride] \n\t"
701 MMI_SDC1(%[ftmp0], %[src], 0x00)
702
703 "daddi %[tmp0], %[tmp0], -0x01 \n\t"
704 PTR_ADDU "%[src], %[src], %[stride] \n\t"
705 "bnez %[tmp0], 1b \n\t"
706 : [ftmp0]"=&f"(ftmp[0]),
707 [tmp0]"=&r"(tmp[0]),
708 RESTRICT_ASM_ALL64
709 [src]"+&r"(src)
710 : [stride]"r"((mips_reg)stride), [srcA]"r"((mips_reg)(src-stride))
711 : "memory"
712 );
713}
714
715void ff_pred8x16_horizontal_8_mmi(uint8_t *src, ptrdiff_t stride)
716{
717 uint64_t tmp[3];
718 mips_reg addr[2];
719
720 __asm__ volatile (
721 PTR_ADDI "%[addr0], %[src], -0x01 \n\t"
722 PTR_ADDU "%[addr1], %[src], $0 \n\t"
723 "dli %[tmp0], 0x08 \n\t"
724 "1: \n\t"
725 "lbu %[tmp1], 0x00(%[addr0]) \n\t"
726 "dmul %[tmp2], %[tmp1], %[ff_pb_1] \n\t"
727 "swl %[tmp2], 0x07(%[addr1]) \n\t"
728 "swr %[tmp2], 0x00(%[addr1]) \n\t"
729 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
730 PTR_ADDU "%[addr1], %[addr1], %[stride] \n\t"
731 "lbu %[tmp1], 0x00(%[addr0]) \n\t"
732 "dmul %[tmp2], %[tmp1], %[ff_pb_1] \n\t"
733 "swl %[tmp2], 0x07(%[addr1]) \n\t"
734 "swr %[tmp2], 0x00(%[addr1]) \n\t"
735 "daddi %[tmp0], %[tmp0], -0x01 \n\t"
736 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
737 PTR_ADDU "%[addr1], %[addr1], %[stride] \n\t"
738 "bnez %[tmp0], 1b \n\t"
739 : [tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]),
740 [tmp2]"=&r"(tmp[2]),
741 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1])
742 : [src]"r"((mips_reg)src), [stride]"r"((mips_reg)stride),
743 [ff_pb_1]"r"(ff_pb_1)
744 : "memory"
745 );
746}
747
748static inline void pred16x16_plane_compat_mmi(uint8_t *src, int stride,
749 const int svq3, const int rv40)
750{
751 double ftmp[11];
752 uint64_t tmp[6];
753 mips_reg addr[1];
754 DECLARE_VAR_ALL64;
755
756 __asm__ volatile(
757 PTR_SUBU "%[addr0], %[src], %[stride] \n\t"
758 "dli %[tmp0], 0x20 \n\t"
759 "dmtc1 %[tmp0], %[ftmp4] \n\t"
760 MMI_ULDC1(%[ftmp0], %[addr0], -0x01)
761 MMI_ULDC1(%[ftmp2], %[addr0], 0x08)
762 "ssrld %[ftmp1], %[ftmp0], %[ftmp4] \n\t"
763 "ssrld %[ftmp3], %[ftmp2], %[ftmp4] \n\t"
764 "pxor %[ftmp4], %[ftmp4], %[ftmp4] \n\t"
765 "punpcklbh %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
766 "punpcklbh %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
767 "punpcklbh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
768 "punpcklbh %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
769 "pmullh %[ftmp0], %[ftmp0], %[ff_pw_m8tom5] \n\t"
770 "pmullh %[ftmp1], %[ftmp1], %[ff_pw_m4tom1] \n\t"
771 "pmullh %[ftmp2], %[ftmp2], %[ff_pw_1to4] \n\t"
772 "pmullh %[ftmp3], %[ftmp3], %[ff_pw_5to8] \n\t"
773 "paddsh %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
774 "paddsh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
775 "paddsh %[ftmp0], %[ftmp0], %[ftmp1] \n\t"
776 "dli %[tmp0], 0x0e \n\t"
777 "dmtc1 %[tmp0], %[ftmp4] \n\t"
778 "pshufh %[ftmp1], %[ftmp0], %[ftmp4] \n\t"
779 "paddsh %[ftmp0], %[ftmp0], %[ftmp1] \n\t"
780 "dli %[tmp0], 0x01 \n\t"
781 "dmtc1 %[tmp0], %[ftmp4] \n\t"
782 "pshufh %[ftmp1], %[ftmp0], %[ftmp4] \n\t"
783 "paddsh %[ftmp5], %[ftmp0], %[ftmp1] \n\t"
784
785 PTR_ADDIU "%[addr0], %[src], -0x01 \n\t"
786 PTR_SUBU "%[addr0], %[addr0], %[stride] \n\t"
787 "lbu %[tmp2], 0x00(%[addr0]) \n\t"
788 "lbu %[tmp5], 0x10(%[addr0]) \n\t"
789 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
790 "lbu %[tmp3], 0x00(%[addr0]) \n\t"
791 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
792 "lbu %[tmp4], 0x00(%[addr0]) \n\t"
793 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
794 "lbu %[tmp0], 0x00(%[addr0]) \n\t"
795 "dsll %[tmp3], %[tmp3], 0x10 \n\t"
796 "dsll %[tmp4], %[tmp4], 0x20 \n\t"
797 "dsll %[tmp0], %[tmp0], 0x30 \n\t"
798 "or %[tmp4], %[tmp4], %[tmp0] \n\t"
799 "or %[tmp2], %[tmp2], %[tmp3] \n\t"
800 "or %[tmp2], %[tmp2], %[tmp4] \n\t"
801 "dmtc1 %[tmp2], %[ftmp0] \n\t"
802
803 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
804 "lbu %[tmp2], 0x00(%[addr0]) \n\t"
805 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
806 "lbu %[tmp3], 0x00(%[addr0]) \n\t"
807 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
808 "lbu %[tmp4], 0x00(%[addr0]) \n\t"
809 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
810 "lbu %[tmp0], 0x00(%[addr0]) \n\t"
811 "dsll %[tmp3], %[tmp3], 0x10 \n\t"
812 "dsll %[tmp4], %[tmp4], 0x20 \n\t"
813 "dsll %[tmp0], %[tmp0], 0x30 \n\t"
814 "or %[tmp4], %[tmp4], %[tmp0] \n\t"
815 "or %[tmp2], %[tmp2], %[tmp3] \n\t"
816 "or %[tmp2], %[tmp2], %[tmp4] \n\t"
817 "dmtc1 %[tmp2], %[ftmp1] \n\t"
818
819 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
820 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
821 "lbu %[tmp2], 0x00(%[addr0]) \n\t"
822 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
823 "lbu %[tmp3], 0x00(%[addr0]) \n\t"
824 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
825 "lbu %[tmp4], 0x00(%[addr0]) \n\t"
826 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
827 "lbu %[tmp0], 0x00(%[addr0]) \n\t"
828 "dsll %[tmp3], %[tmp3], 0x10 \n\t"
829 "dsll %[tmp4], %[tmp4], 0x20 \n\t"
830 "dsll %[tmp0], %[tmp0], 0x30 \n\t"
831 "or %[tmp4], %[tmp4], %[tmp0] \n\t"
832 "or %[tmp2], %[tmp2], %[tmp3] \n\t"
833 "or %[tmp2], %[tmp2], %[tmp4] \n\t"
834 "dmtc1 %[tmp2], %[ftmp2] \n\t"
835
836 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
837 "lbu %[tmp2], 0x00(%[addr0]) \n\t"
838 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
839 "lbu %[tmp3], 0x00(%[addr0]) \n\t"
840 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
841 "lbu %[tmp4], 0x00(%[addr0]) \n\t"
842 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
843 "lbu %[tmp0], 0x00(%[addr0]) \n\t"
844 "daddu %[tmp5], %[tmp5], %[tmp0] \n\t"
845 "daddiu %[tmp5], %[tmp5], 0x01 \n\t"
846 "dsll %[tmp5], %[tmp5], 0x04 \n\t"
847
848 "dsll %[tmp3], %[tmp3], 0x10 \n\t"
849 "dsll %[tmp4], %[tmp4], 0x20 \n\t"
850 "dsll %[tmp0], %[tmp0], 0x30 \n\t"
851 "or %[tmp4], %[tmp4], %[tmp0] \n\t"
852 "or %[tmp2], %[tmp2], %[tmp3] \n\t"
853 "or %[tmp2], %[tmp2], %[tmp4] \n\t"
854 "dmtc1 %[tmp2], %[ftmp3] \n\t"
855
856 "pmullh %[ftmp0], %[ftmp0], %[ff_pw_m8tom5] \n\t"
857 "pmullh %[ftmp1], %[ftmp1], %[ff_pw_m4tom1] \n\t"
858 "pmullh %[ftmp2], %[ftmp2], %[ff_pw_1to4] \n\t"
859 "pmullh %[ftmp3], %[ftmp3], %[ff_pw_5to8] \n\t"
860 "paddsh %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
861 "paddsh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
862 "paddsh %[ftmp0], %[ftmp0], %[ftmp1] \n\t"
863 "dli %[tmp0], 0x0e \n\t"
864 "dmtc1 %[tmp0], %[ftmp4] \n\t"
865 "pshufh %[ftmp1], %[ftmp0], %[ftmp4] \n\t"
866 "paddsh %[ftmp0], %[ftmp0], %[ftmp1] \n\t"
867
868 "dli %[tmp0], 0x01 \n\t"
869 "dmtc1 %[tmp0], %[ftmp4] \n\t"
870 "pshufh %[ftmp1], %[ftmp0], %[ftmp4] \n\t"
871 "paddsh %[ftmp6], %[ftmp0], %[ftmp1] \n\t"
872
873 "dmfc1 %[tmp0], %[ftmp5] \n\t"
874 "dsll %[tmp0], %[tmp0], 0x30 \n\t"
875 "dsra %[tmp0], %[tmp0], 0x30 \n\t"
876 "dmfc1 %[tmp1], %[ftmp6] \n\t"
877 "dsll %[tmp1], %[tmp1], 0x30 \n\t"
878 "dsra %[tmp1], %[tmp1], 0x30 \n\t"
879
880 "beqz %[svq3], 1f \n\t"
881 "dli %[tmp2], 0x04 \n\t"
882 "ddiv %[tmp0], %[tmp0], %[tmp2] \n\t"
883 "ddiv %[tmp1], %[tmp1], %[tmp2] \n\t"
884 "dli %[tmp2], 0x05 \n\t"
885 "dmul %[tmp0], %[tmp0], %[tmp2] \n\t"
886 "dmul %[tmp1], %[tmp1], %[tmp2] \n\t"
887 "dli %[tmp2], 0x10 \n\t"
888 "ddiv %[tmp0], %[tmp0], %[tmp2] \n\t"
889 "ddiv %[tmp1], %[tmp1], %[tmp2] \n\t"
890 "daddu %[tmp2], %[tmp0], $0 \n\t"
891 "daddu %[tmp0], %[tmp1], $0 \n\t"
892 "daddu %[tmp1], %[tmp2], $0 \n\t"
893 "b 2f \n\t"
894
895 "1: \n\t"
896 "beqz %[rv40], 1f \n\t"
897 "dsra %[tmp2], %[tmp0], 0x02 \n\t"
898 "daddu %[tmp0], %[tmp0], %[tmp2] \n\t"
899 "dsra %[tmp2], %[tmp1], 0x02 \n\t"
900 "daddu %[tmp1], %[tmp1], %[tmp2] \n\t"
901 "dsra %[tmp0], %[tmp0], 0x04 \n\t"
902 "dsra %[tmp1], %[tmp1], 0x04 \n\t"
903 "b 2f \n\t"
904
905 "1: \n\t"
906 "dli %[tmp2], 0x05 \n\t"
907 "dmul %[tmp0], %[tmp0], %[tmp2] \n\t"
908 "dmul %[tmp1], %[tmp1], %[tmp2] \n\t"
909 "daddiu %[tmp0], %[tmp0], 0x20 \n\t"
910 "daddiu %[tmp1], %[tmp1], 0x20 \n\t"
911 "dsra %[tmp0], %[tmp0], 0x06 \n\t"
912 "dsra %[tmp1], %[tmp1], 0x06 \n\t"
913
914 "2: \n\t"
915 "daddu %[tmp3], %[tmp0], %[tmp1] \n\t"
916 "dli %[tmp2], 0x07 \n\t"
917 "dmul %[tmp3], %[tmp3], %[tmp2] \n\t"
918 "dsubu %[tmp5], %[tmp5], %[tmp3] \n\t"
919
920 "pxor %[ftmp4], %[ftmp4], %[ftmp4] \n\t"
921 "dmtc1 %[tmp0], %[ftmp0] \n\t"
922 "pshufh %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
923 "dmtc1 %[tmp1], %[ftmp5] \n\t"
924 "pshufh %[ftmp5], %[ftmp5], %[ftmp4] \n\t"
925 "dmtc1 %[tmp5], %[ftmp6] \n\t"
926 "pshufh %[ftmp6], %[ftmp6], %[ftmp4] \n\t"
927 "dli %[tmp0], 0x05 \n\t"
928 "dmtc1 %[tmp0], %[ftmp7] \n\t"
929 "pmullh %[ftmp1], %[ff_pw_0to3], %[ftmp0] \n\t"
930 "dmtc1 %[ff_pw_4to7], %[ftmp2] \n\t"
931 "pmullh %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
932 "dmtc1 %[ff_pw_8tob], %[ftmp3] \n\t"
933 "pmullh %[ftmp3], %[ftmp3], %[ftmp0] \n\t"
934 "dmtc1 %[ff_pw_ctof], %[ftmp4] \n\t"
935 "pmullh %[ftmp4], %[ftmp4], %[ftmp0] \n\t"
936
937 "dli %[tmp0], 0x10 \n\t"
938 PTR_ADDU "%[addr0], %[src], $0 \n\t"
939 "1: \n\t"
940 "paddsh %[ftmp8], %[ftmp1], %[ftmp6] \n\t"
941 "psrah %[ftmp8], %[ftmp8], %[ftmp7] \n\t"
942 "paddsh %[ftmp9], %[ftmp2], %[ftmp6] \n\t"
943 "psrah %[ftmp9], %[ftmp9], %[ftmp7] \n\t"
944 "packushb %[ftmp0], %[ftmp8], %[ftmp9] \n\t"
945 MMI_SDC1(%[ftmp0], %[addr0], 0x00)
946
947 "paddsh %[ftmp8], %[ftmp3], %[ftmp6] \n\t"
948 "psrah %[ftmp8], %[ftmp8], %[ftmp7] \n\t"
949 "paddsh %[ftmp9], %[ftmp4], %[ftmp6] \n\t"
950 "psrah %[ftmp9], %[ftmp9], %[ftmp7] \n\t"
951 "packushb %[ftmp0], %[ftmp8], %[ftmp9] \n\t"
952 MMI_SDC1(%[ftmp0], %[addr0], 0x08)
953
954 "paddsh %[ftmp6], %[ftmp6], %[ftmp5] \n\t"
955 PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
956 "daddiu %[tmp0], %[tmp0], -0x01 \n\t"
957 "bnez %[tmp0], 1b \n\t"
958 : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
959 [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
960 [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
961 [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
962 [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
963 [tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]),
964 [tmp2]"=&r"(tmp[2]), [tmp3]"=&r"(tmp[3]),
965 [tmp4]"=&r"(tmp[4]), [tmp5]"=&r"(tmp[5]),
966 RESTRICT_ASM_ALL64
967 [addr0]"=&r"(addr[0])
968 : [src]"r"(src), [stride]"r"((mips_reg)stride),
969 [svq3]"r"(svq3), [rv40]"r"(rv40),
970 [ff_pw_m8tom5]"f"(ff_pw_m8tom5.f),[ff_pw_m4tom1]"f"(ff_pw_m4tom1.f),
971 [ff_pw_1to4]"f"(ff_pw_1to4.f), [ff_pw_5to8]"f"(ff_pw_5to8.f),
972 [ff_pw_0to3]"f"(ff_pw_0to3.f), [ff_pw_4to7]"r"(ff_pw_4to7.i),
973 [ff_pw_8tob]"r"(ff_pw_8tob.i), [ff_pw_ctof]"r"(ff_pw_ctof.i)
974 : "memory"
975 );
976}
977
978void ff_pred16x16_plane_h264_8_mmi(uint8_t *src, ptrdiff_t stride)
979{
980 pred16x16_plane_compat_mmi(src, stride, 0, 0);
981}
982
983void ff_pred16x16_plane_svq3_8_mmi(uint8_t *src, ptrdiff_t stride)
984{
985 pred16x16_plane_compat_mmi(src, stride, 1, 0);
986}
987
988void ff_pred16x16_plane_rv40_8_mmi(uint8_t *src, ptrdiff_t stride)
989{
990 pred16x16_plane_compat_mmi(src, stride, 0, 1);
991}
PTR_SUBU
#define PTR_SUBU
Definition asmdefs.h:52
PTR_ADDI
#define PTR_ADDI
Definition asmdefs.h:51
PTR_ADDIU
#define PTR_ADDIU
Definition asmdefs.h:50
mips_reg
#define mips_reg
Definition asmdefs.h:46
PTR_ADDU
#define PTR_ADDU
Definition asmdefs.h:49
__asm__
__asm__(".macro parse_r var r\n\t" "\\var = -1\n\t" _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) ".iflt \\var\n\t" ".error \"Unable to parse register name \\r\"\n\t" ".endif\n\t" ".endm")
PTR_SRL
#define PTR_SRL
Definition asmdefs.h:56
bit_depth_template.c
h264pred_mips.h
ff_pred16x16_plane_svq3_8_mmi
void ff_pred16x16_plane_svq3_8_mmi(uint8_t *src, ptrdiff_t stride)
Definition h264pred_mmi.c:983
ff_pred16x16_dc_8_mmi
void ff_pred16x16_dc_8_mmi(uint8_t *src, ptrdiff_t stride)
Definition h264pred_mmi.c:98
pred16x16_plane_compat_mmi
static void pred16x16_plane_compat_mmi(uint8_t *src, int stride, const int svq3, const int rv40)
Definition h264pred_mmi.c:748
ff_pred8x8_dc_8_mmi
void ff_pred8x8_dc_8_mmi(uint8_t *src, ptrdiff_t stride)
Definition h264pred_mmi.c:578
ff_pred16x16_horizontal_8_mmi
void ff_pred16x16_horizontal_8_mmi(uint8_t *src, ptrdiff_t stride)
Definition h264pred_mmi.c:61
ff_pred8x8_horizontal_8_mmi
void ff_pred8x8_horizontal_8_mmi(uint8_t *src, ptrdiff_t stride)
Definition h264pred_mmi.c:493
ff_pred8x8_top_dc_8_mmi
void ff_pred8x8_top_dc_8_mmi(uint8_t *src, ptrdiff_t stride)
Definition h264pred_mmi.c:526
ff_pred8x16_horizontal_8_mmi
void ff_pred8x16_horizontal_8_mmi(uint8_t *src, ptrdiff_t stride)
Definition h264pred_mmi.c:715
ff_pred4x4_dc_8_mmi
void ff_pred4x4_dc_8_mmi(uint8_t *src, const uint8_t *topright, ptrdiff_t stride)
Definition h264pred_mmi.c:436
ff_pred8x8l_vertical_8_mmi
void ff_pred8x8l_vertical_8_mmi(uint8_t *src, int has_topleft, int has_topright, ptrdiff_t stride)
Definition h264pred_mmi.c:354
ff_pred16x16_plane_rv40_8_mmi
void ff_pred16x16_plane_rv40_8_mmi(uint8_t *src, ptrdiff_t stride)
Definition h264pred_mmi.c:988
ff_pred16x16_plane_h264_8_mmi
void ff_pred16x16_plane_h264_8_mmi(uint8_t *src, ptrdiff_t stride)
Definition h264pred_mmi.c:978
ff_pred8x16_vertical_8_mmi
void ff_pred8x16_vertical_8_mmi(uint8_t *src, ptrdiff_t stride)
Definition h264pred_mmi.c:684
ff_pred8x8l_dc_8_mmi
void ff_pred8x8l_dc_8_mmi(uint8_t *src, int has_topleft, int has_topright, ptrdiff_t stride)
Definition h264pred_mmi.c:247
ff_pred16x16_vertical_8_mmi
void ff_pred16x16_vertical_8_mmi(uint8_t *src, ptrdiff_t stride)
Definition h264pred_mmi.c:31
ff_pred8x8_vertical_8_mmi
void ff_pred8x8_vertical_8_mmi(uint8_t *src, ptrdiff_t stride)
Definition h264pred_mmi.c:466
ff_pred8x8l_top_dc_8_mmi
void ff_pred8x8l_top_dc_8_mmi(uint8_t *src, int has_topleft, int has_topright, ptrdiff_t stride)
Definition h264pred_mmi.c:156
svq3
ptrdiff_t const int svq3
Definition h264pred_template.c:412
rv40
ptrdiff_t const int const int rv40
Definition h264pred_template.c:414
ff_pw_4to7
const union av_intfloat64 ff_pw_4to7
Definition constants.c:52
ff_pw_8tob
const union av_intfloat64 ff_pw_8tob
Definition constants.c:53
ff_pw_1to4
const union av_intfloat64 ff_pw_1to4
Definition constants.c:49
ff_pw_m8tom5
const union av_intfloat64 ff_pw_m8tom5
Definition constants.c:47
ff_pw_ctof
const union av_intfloat64 ff_pw_ctof
Definition constants.c:54
ff_pw_5to8
const union av_intfloat64 ff_pw_5to8
Definition constants.c:50
ff_pw_m4tom1
const union av_intfloat64 ff_pw_m4tom1
Definition constants.c:48
ff_pw_0to3
const union av_intfloat64 ff_pw_0to3
Definition constants.c:51
ff_pw_2
const union av_intfloat64 ff_pw_2
Definition constants.c:26
ff_pb_1
const union av_intfloat64 ff_pb_1
Definition constants.c:58
RESTRICT_ASM_ALL64
#define RESTRICT_ASM_ALL64
Definition mmiutils.h:40
DECLARE_VAR_ADDRT
#define DECLARE_VAR_ADDRT
Definition mmiutils.h:41
DECLARE_VAR_ALL64
#define DECLARE_VAR_ALL64
Definition mmiutils.h:39
RESTRICT_ASM_ADDRT
#define RESTRICT_ASM_ADDRT
Definition mmiutils.h:42
stride
#define stride
Definition h264pred_template.c:536
tmp
static uint8_t tmp[40]
Definition aes_ctr.c:52
src1
#define src1
Definition h264pred.c:141
src0
#define src0
Definition h264pred.c:140
src
#define src
Definition vp8dsp.c:248
av_intfloat64
Definition intfloat.h:32
av_intfloat64::f
double f
Definition intfloat.h:34
av_intfloat64::i
uint64_t i
Definition intfloat.h:33
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